| | 1 | = SFP-Ethernet Design = |
| | 2 | |
| | 3 | This design provides an example of using the SFP MGT interfaces on the WARP FPGA Board v2.2 as gigabit Ethernet interfaces. |
| | 4 | |
| | 5 | '''Requirements:''' |
| | 6 | * WARP FPGA Board v2.2 |
| | 7 | * 1 or 2 SFP 1000Base-T Ethernet modules in MGTs 7 and 8 |
| | 8 | * Xilinx EDK 10.1.03 or 11.3 |
| | 9 | |
| | 10 | [[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:sfpEthernet_blockDiagram.jpg)]] |
| | 11 | |
| | 12 | '''Important Details''' |
| | 13 | * The xps_ll_temac pcore has two ports for LocalLink clocks (LlinkTemac0_CLK and LlinkTemac1_CLK). These must be connected to the same clock signal which drives the SPLB_CLK ports on the corresponding xps_ll_fifo pcores. These signals are not connected automatically when you connect the LocalLink bus interfaces on the TEMAC and FIFO. |
| | 14 | * The TEMAC PHY type must be set to 1000Base-T (C_PHY_TYPE = 5). The other MGT-compatible PHY type (SGMII) didn't work with our SFP Ethernet modules. |
| | 15 | * The DCLK port on the xps_ll_temac core should be connected to a clock signal with frequency between 25 and 50MHz. It's unclear whether this signal is absolutely required for 1000Base-T modes (the Xilinx documentation is frustratingly vague), but our designs worked fine with a 40MHz DCLK. |
