| | 1 | [[TracNav(HardwareUsersGuides/FPGABoard_v2.2/TOC)]] |
| | 2 | |
| | 3 | == WARP FPGA Board Memory Resources == |
| | 4 | |
| | 5 | === On-Chip Memory === |
| | 6 | The V4 FX100 FPGA provides 376 18kb RAM blocks (6.7Mb total). Logic slices can also be used as RAM (what XIlinx calls ''distributed memory''); the FX100 provides up to 659kb of distributed memory. |
| | 7 | |
| | 8 | === DDR2 SO-DIMM === |
| | 9 | The WARP FPGA Board v2.2 includes a DDR2 SO-DIMM slot. This connector is routed to dedicated FPGA I/O and clocking resources and supports up to 2GB modules. |
| | 10 | |
| | 11 | In order to use a SO-DIMM, the user FPGA design must include a DDR2 memory controller. Thankfully, Xilinx provides (and maintains) a high performance controller as part of their Multi-Port Memory Controller (MPMC). |
| | 12 | |
| | 13 | [[Image(HardwareUsersGuides/FPGABoard_v1.2/Images:FPGA_Board_SRAM.jpg, align=right)]] |
| | 14 | |
| | 15 | |
| | 16 | === More Resources === |
| | 17 | * [http://www.xilinx.com/products/ipcenter/mpmc.htm Xilinx MPMC IP] |
| | 18 | * [http://www.xilinx.com/support/documentation/ip_documentation/mpmc.pdf Xilinx MPMC Datasheet] |
