wiki:HardwareUsersGuides/FPGABoard_v2.2/Memory

Version 4 (modified by sgupta, 14 years ago) (diff)

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WARP FPGA Board Memory Resources

On-Chip Memory

The V4 FX100 FPGA provides 376 18kb RAM blocks (6.7Mb total). Logic slices can also be used as RAM (what XIlinx calls distributed memory); the FX100 provides up to 659kb of distributed memory.

DDR2 SO-DIMM

The WARP FPGA Board v2.2 includes a DDR2 SO-DIMM slot. This connector is routed to dedicated FPGA I/O and clocking resources and supports up to 2GB modules.

FPGA Board SO-DIMM slot (shown with 2GB SO-DIMM installed)

In order to use the SO-DIMM, the user FPGA design must include a DDR2 memory controller. Thankfully, Xilinx provides (and maintains) a high performance controller as part of their Multi-Port Memory Controller (MPMC).

We have verified the MPMC in EDK 10.1.03 and 11.3 using a 2GB SO-DIMM from Crucial (part CT25664AC667). Other modules should be compatible, but may require customization of the MPMC parameters.

There are a large number of pins and parameters involved in instantiating the MPMC in a design. We strongly recommend using Base System builder and our XBD file to generate MPMC designs. The MHS snippet below is an example instantiation (for EDK 10.1.03).

EGIN mpmc
 PARAMETER INSTANCE = DDR2_SDRAM_2GB
 PARAMETER HW_VER = 4.03.a
 PARAMETER C_NUM_PORTS = 2
 PARAMETER C_MEM_PARTNO = MT16HTF25664H-667
 PARAMETER C_MEM_TYPE = DDR2
 PARAMETER C_NUM_IDELAYCTRL = 4
 PARAMETER C_IDELAYCTRL_LOC = IDELAYCTRL_X0Y0-IDELAYCTRL_X0Y1-IDELAYCTRL_X2Y1-IDELAYCTRL_X2Y0
 PARAMETER C_MEM_DQS_WIDTH = 8
 PARAMETER C_MEM_DM_WIDTH = 8
 PARAMETER C_MEM_ADDR_WIDTH = 14
 PARAMETER C_MEM_BANKADDR_WIDTH = 3
 PARAMETER C_PIM0_BASETYPE = 2
 PARAMETER C_PIM1_BASETYPE = 2
 PARAMETER C_MPMC_CLK0_PERIOD_PS = 6250
 PARAMETER C_MPMC_BASEADDR = 0x00000000
 PARAMETER C_MPMC_HIGHADDR = 0x7fffffff
 BUS_INTERFACE SPLB0 = ppc405_0_iplb1
 BUS_INTERFACE SPLB1 = ppc405_0_dplb1
 PORT DDR2_Addr = fpga_0_DDR2_SDRAM_2GB_DDR2_Addr
 PORT DDR2_BankAddr = fpga_0_DDR2_SDRAM_2GB_DDR2_BankAddr
 PORT DDR2_CAS_n = fpga_0_DDR2_SDRAM_2GB_DDR2_CAS_n
 PORT DDR2_CE = fpga_0_DDR2_SDRAM_2GB_DDR2_CE
 PORT DDR2_CS_n = fpga_0_DDR2_SDRAM_2GB_DDR2_CS_n
 PORT DDR2_RAS_n = fpga_0_DDR2_SDRAM_2GB_DDR2_RAS_n
 PORT DDR2_WE_n = fpga_0_DDR2_SDRAM_2GB_DDR2_WE_n
 PORT DDR2_DM = fpga_0_DDR2_SDRAM_2GB_DDR2_DM
 PORT DDR2_DQS = fpga_0_DDR2_SDRAM_2GB_DDR2_DQS
 PORT DDR2_DQS_n = fpga_0_DDR2_SDRAM_2GB_DDR2_DQS_n
 PORT DDR2_DQ = fpga_0_DDR2_SDRAM_2GB_DDR2_DQ
 PORT DDR2_Clk = fpga_0_DDR2_SDRAM_2GB_DDR2_Clk
 PORT DDR2_Clk_n = fpga_0_DDR2_SDRAM_2GB_DDR2_Clk_n
 PORT DDR2_ODT = fpga_0_DDR2_SDRAM_2GB_DDR2_ODT
 PORT MPMC_Clk0 = proc_clk_s
 PORT MPMC_Clk90 = DDR2_SDRAM_2GB_mpmc_clk_90_s
 PORT MPMC_Clk_200MHz = clk_200mhz_s
 PORT MPMC_Rst = sys_periph_reset
END

Constraints

# FPGA Board v2.2 constraints for 2GB DDR2 SO-DIMM
#
# The memory slot (J57) is located on the bottom of the FPGA Board.
# The constraints are for a 2GB memory that is 64-bit wide with a 14-bit address
#
Net DDR2_SDRAM_2GB_Addr_pin<0> LOC = AH13 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_Addr_pin<1> LOC = AR16 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_Addr_pin<2> LOC = AH14 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_Addr_pin<3> LOC = AU13 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_Addr_pin<4> LOC = AP25 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_Addr_pin<5> LOC = AN30 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_Addr_pin<6> LOC = AR29 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_Addr_pin<7> LOC = AT29 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_Addr_pin<8> LOC = AL30 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_Addr_pin<9> LOC = AP30 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_Addr_pin<10> LOC = AM30 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_Addr_pin<11> LOC = AL29 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_Addr_pin<12> LOC = AN29 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_Addr_pin<13> LOC = AK29 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_BankAddr_pin<0> LOC = AP14 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_BankAddr_pin<1> LOC = AN13 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_BankAddr_pin<2> LOC = AT14 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_CAS_n_pin LOC = AU12 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_CE_pin<0> LOC = AP16 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_CE_pin<1> LOC = AK11 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_CS_n_pin<0> LOC = AK14 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_CS_n_pin<1> LOC = AT13 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_RAS_n_pin LOC = AJ11 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_WE_n_pin LOC = AR13 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_DM_pin<0> LOC = AU36 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_DM_pin<1> LOC = AR34 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_DM_pin<2> LOC = AK31 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_DM_pin<3> LOC = AN28 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_DM_pin<4> LOC = AU16 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_DM_pin<5> LOC = AP12 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_DM_pin<6> LOC = AP15 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_DM_pin<7> LOC = AJ12 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_DQS<0> LOC = AU26 | IOSTANDARD = DIFF_SSTL18_II;
Net DDR2_SDRAM_2GB_DQS<1> LOC = AT35 | IOSTANDARD = DIFF_SSTL18_II;
Net DDR2_SDRAM_2GB_DQS<2> LOC = AM28 | IOSTANDARD = DIFF_SSTL18_II;
Net DDR2_SDRAM_2GB_DQS<3> LOC = AT31 | IOSTANDARD = DIFF_SSTL18_II;
Net DDR2_SDRAM_2GB_DQS<4> LOC = AN8 | IOSTANDARD = DIFF_SSTL18_II;
Net DDR2_SDRAM_2GB_DQS<5> LOC = AT15 | IOSTANDARD = DIFF_SSTL18_II;
Net DDR2_SDRAM_2GB_DQS<6> LOC = AT11 | IOSTANDARD = DIFF_SSTL18_II;
Net DDR2_SDRAM_2GB_DQS<7> LOC = AL13 | IOSTANDARD = DIFF_SSTL18_II;
Net DDR2_SDRAM_2GB_DQS_n<0> LOC = AT26 | IOSTANDARD = DIFF_SSTL18_II;
Net DDR2_SDRAM_2GB_DQS_n<1> LOC = AU35 | IOSTANDARD = DIFF_SSTL18_II;
Net DDR2_SDRAM_2GB_DQS_n<2> LOC = AL28 | IOSTANDARD = DIFF_SSTL18_II;
Net DDR2_SDRAM_2GB_DQS_n<3> LOC = AU31 | IOSTANDARD = DIFF_SSTL18_II;
Net DDR2_SDRAM_2GB_DQS_n<4> LOC = AN7 | IOSTANDARD = DIFF_SSTL18_II;
Net DDR2_SDRAM_2GB_DQS_n<5> LOC = AU15 | IOSTANDARD = DIFF_SSTL18_II;
Net DDR2_SDRAM_2GB_DQS_n<6> LOC = AU11 | IOSTANDARD = DIFF_SSTL18_II;
Net DDR2_SDRAM_2GB_DQS_n<7> LOC = AM13 | IOSTANDARD = DIFF_SSTL18_II;
Net DDR2_SDRAM_2GB_DQ<0> LOC = AR27 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_DQ<1> LOC = AR26 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_DQ<2> LOC = AM26 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_DQ<3> LOC = AT24 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_DQ<4> LOC = AP37 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_DQ<5> LOC = AR37 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_DQ<6> LOC = AP32 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_DQ<7> LOC = AT36 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_DQ<8> LOC = AR33 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_DQ<9> LOC = AR24 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_DQ<10> LOC = AM32 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_DQ<11> LOC = AN32 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_DQ<12> LOC = AR36 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_DQ<13> LOC = AT34 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_DQ<14> LOC = AP36 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_DQ<15> LOC = AP26 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_DQ<16> LOC = AM31 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_DQ<17> LOC = AL31 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_DQ<18> LOC = AU28 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_DQ<19> LOC = AP24 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_DQ<20> LOC = AR32 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_DQ<21> LOC = AP31 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_DQ<22> LOC = AU33 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_DQ<23> LOC = AM27 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_DQ<24> LOC = AT33 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_DQ<25> LOC = AU27 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_DQ<26> LOC = AN27 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_DQ<27> LOC = AR31 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_DQ<28> LOC = AU32 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_DQ<29> LOC = AU30 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_DQ<30> LOC = AT30 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_DQ<31> LOC = AT28 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_DQ<32> LOC = AR11 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_DQ<33> LOC = AL10 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_DQ<34> LOC = AP10 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_DQ<35> LOC = AR8 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_DQ<36> LOC = AT18 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_DQ<37> LOC = AU17 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_DQ<38> LOC = AH12 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_DQ<39> LOC = AR14 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_DQ<40> LOC = AR12 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_DQ<41> LOC = AP7 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_DQ<42> LOC = AR9 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_DQ<43> LOC = AT9 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_DQ<44> LOC = AL14 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_DQ<45> LOC = AL11 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_DQ<46> LOC = AJ14 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_DQ<47> LOC = AM15 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_DQ<48> LOC = AM10 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_DQ<49> LOC = AP9 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_DQ<50> LOC = AT8 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_DQ<51> LOC = AL9 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_DQ<52> LOC = AN15 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_DQ<53> LOC = AN12 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_DQ<54> LOC = AN14 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_DQ<55> LOC = AK13 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_DQ<56> LOC = AK9 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_DQ<57> LOC = AU8 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_DQ<58> LOC = AR7 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_DQ<59> LOC = AJ10 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_DQ<60> LOC = AK12 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_DQ<61> LOC = AN10 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_DQ<62> LOC = AT10 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_DQ<63> LOC = AU10 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_Clk_pin<0> LOC = AP35 | IOSTANDARD = DIFF_SSTL18_II;
Net DDR2_SDRAM_2GB_Clk_pin<1> LOC = AK27 | IOSTANDARD = DIFF_SSTL18_II;
Net DDR2_SDRAM_2GB_Clk_n_pin<0> LOC = AP34 | IOSTANDARD = DIFF_SSTL18_II;
Net DDR2_SDRAM_2GB_Clk_n_pin<1> LOC = AL26 | IOSTANDARD = DIFF_SSTL18_II;
Net DDR2_SDRAM_2GB_ODT_pin<0> LOC = AT16 | IOSTANDARD = SSTL18_I;
Net DDR2_SDRAM_2GB_ODT_pin<1> LOC = AP11 | IOSTANDARD = SSTL18_I;

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