Changes between Version 1 and Version 2 of HardwareUsersGuides/WARPv3/Ethernet
- Timestamp:
- Nov 13, 2012, 11:02:36 PM (12 years ago)
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HardwareUsersGuides/WARPv3/Ethernet
v1 v2 8 8 9 9 Each PHY also has a dedicated MDIO port for exchanging configuration information with the Ethernet MAC. Each MDIO port is connected to dedicated FPGA pins for totally independent operation of the two interfaces. MDIO access requires a 5-bit address, which is different for the two PHYs: 10 * ETH A MDIO address: 0b00110 11 * ETH B MDIO address: 0b00111 10 * ETH A MDIO address: 0b00110 (0x6) 11 * ETH B MDIO address: 0b00111 (0x7) 12 12 13 13 The FPGA pin constraints for the Ethernet interfaces are listed below. … … 21 21 #88E1121R PHY 1 = ETH A on WARP v3 Board 22 22 NET "ETH_A_INT" LOC = "C10" | IOSTANDARD = "LVCMOS25"; 23 NET "ETH_A_MDC" LOC = "A P9" | IOSTANDARD = "LVCMOS25";23 NET "ETH_A_MDC" LOC = "AK8" | IOSTANDARD = "LVCMOS25"; #errata: labeled MDIO in schematics, pulled up 24 24 NET "ETH_A_PD" LOC = "K9" | IOSTANDARD = "LVCMOS25"; 25 NET "ETH_A_MDIO" LOC = "A K8" | IOSTANDARD = "LVCMOS25";25 NET "ETH_A_MDIO" LOC = "AP9" | IOSTANDARD = "LVCMOS25" | PULLUP; #errata: labeled MDC in schematics 26 26 NET "ETH_A_RX_CLK" LOC = "AC10" | IOSTANDARD = "LVCMOS25"; 27 27 NET "ETH_A_RX_CTRL" LOC = "AL9" | IOSTANDARD = "LVCMOS25";