[[TracNav(HardwareUsersGuides/WARPv3/TOC)]]
= WARP v3 User Guide: FMC Slot =
The WARP v3 board implements a high-pin count (HPC) FMC carrier slot. For details on the FMC standard, refer to [http://www.vita.com/fmc.html VITA specification 57.1]. The details of the WARP v3 FMC implementation are described below.

|| [[Image(wiki:HardwareUsersGuides/WARPv3/files:important.png,nolink,valign=middle)]] || Always disconnect the WARP v3 board power supply before mounting/removing an FMC module. The external 12VDC is routed directly to the FMC connector, even when the power switch is off.[[BR]][[BR]]Be careful when inserting FMC modules. '''DO NOT''' simply press down on the module, thereby flexing the WARP v3 board. It is essential to support both sides of the board when inserting a module. We recommend "pinching" the module into place from both sides of the boards, with fingers/thumbs on opposite sides of the FMC connector. Refer to the [wiki:howto/FMC_Module_Handling FMC module howto] for an illustration. [[BR]][[BR]]Damage to the WARP v3 components or PCB resulting from mechanical strain is not covered by warranty. ||

== Signal Connections ==
The FMC specification provides multiple banks of signals which can be connected to the FPGA on a carrier board.  The WARP v3 FMC implementation connects all required and most optional signals.

'''FPGA general purpose I/O:'''
 * 156 general purpose FPGA I/O are connected to the FMC slot
  * FMC LA: Fully connected - 34 differential pairs (68 I/O)
  * FMC HA: Fully connected - 24 differential pairs (48 I/O)
  * FMC HB: 
   * HB![0:19] connected - 20 differential pairs (40 I/O)
   * HB![20:21] unconnected
 * All LA, HA signals must use 2.5v I/O
 * HB signals use VCCO driven by FMC module
 * All LA, HA, HB signals must use IOSTANDARDs which require no external VREF

'''FPGA multi-gigabit transceivers:'''
 * 8 MGTs connected to FMC DP![0:7]
 * FMC DP![8:9] unconnected
 * Both M2C MGT reference clocks connected (GBTCLK![0:1]_p/n)

'''FMC Clock signals:'''
 * CLK0_M2C and CLK1_M2C connected to FPGA global clock pins
 * CLK2_BIDIR and CLK3_BIDIR driven by WARP v3 RF interface clock buffers
 * All LA, HA, HB CC signals are connected to FPGA MRCC or SRCC pins in FPGA columns 2 or 3

'''Power:'''
 * All required voltage rails provided (12v, 3.3v, 2.5v)
 * FMC VADJ fixed at 2.5v
 * FMC VIO_B_M2C connected to VCCO for FPGA bank 36 (only bank with HB I/O connections)
 * FMC VREF_A_M2C and VREF_B_M2C are unconnected

'''Misc:'''
 * FMC JTAG pins connected to 3.3v JTAG chain
 * FMC IIC EEPROM pins connected to 3.3v FPGA I/O (via 2.5v-3.3v level shifting)

The sections below describe the WARP v3 FMC implementation in detail.
----

== FPGA I/O ==
The FMC LA, HA and HB banks are connected to general purpose FPGA pins in I/O banks 24, 25, 26, 35 and 36. Every signal is routed as half of a differential pair according to the mapping defined in the FMC spec. The _p and _n halves of each pair are connected to _p and _n FPGA I/O.

All 156 signals are connected directly to FPGA pins with no termination on the WARP v3 board. You must use the FPGA's internal LVDS termination for any differential pair driven by an FMC module.

In order to maximize signal integrity, every FMC I/O trace is routed on exactly one internal layer with only two vias (to connect to the FMC and FPGA pins). Every FMC routing layer is directly adjacent to a solid ground plane.

The length of the p and n traces in each differential pair are well matched. The trace lengths in each bank are matched to the ranges listed below.
  ||= Bank =||= Min Length =||= Max Length =||
  || LA || 0.867" || 1.277" ||
  || HA || 0.830" || 1.493" ||
  || HB || 0.957" || 1.853" ||

== Clocks ==
The FMC spec defines four dedicated differential clock signals:
 * CLK![0:1]_M2C_p/n: Always driven by the FMC module into the carrier board's FPGA
 * CLK![2:3]_BIDIR_p/n: Driven by either the carrier board or FMC module

The WARP v3 FMC implementation connections CLK![0:1]_M2C to FPGA GCLK pins, as listed below.
  ||= FMC CLK =||= FPGA Pin =||
  || CLK0_M2C_P || K24 ||
  || CLK0_M2C_N || K23 ||
  || CLK1_M2C_P || L23 ||
  || CLK1_M2C_N || M22 ||

The FMC CLK![2:3]_BIDIR signals are always driven by the WARP v3 board and must either be unconnected or routed to IC inputs on the FMC module. The WARP v3 FMC implementaton uses these clock signals to drive copies of the RF interface clocks to an FMC module. This will enable RF circuits on an FMC module to be synchronized with the integrated RF interfaces without any external cabling. The CLK![2:3]_BIDIR connections are listed below.

  ||= FMC CLK =||= WARP v3 Signal =||= WARP v3 Connection =||
  || CLK2_BIDIR || Sampling Clock || U46.CLKOUT4 ||
  || CLK3_BIDIR || RF Reference Clock || U20.CLKOUT4 ||

Both CLK![2:3]_BIDIR signals are driven by LVDS outputs on the AD9512 clock buffers. The FMC module must implement far-end LVDS termination. 

In addition to the dedicated clock signals, the FMC spec recommends a subset of each I/O bank be tied to clock-capable pins on the carrier FPGA. The WARP v3 FMC implementation connects all recommended CC I/O to column 2 or 3 CC pins on the FPGA. The details are listed below.

  ||= FMC I/O =||= FPGA p/n Pins =||= FPGA Pin Type =||
  ||LA![0]_CC || F21/G20 || MRCC ||
  ||LA![1]_CC || B20/C19 || MRCC ||
  ||LA![17]_CC || L13/M13 || MRCC ||
  ||LA![18]_CC || M12/M11 || MRCC ||
  ||HA![0]_CC || C28/B28 || MRCC ||
  ||HA![1]_CC || C29/D29 || MRCC ||
  ||HA![17]_CC || F25/G25 || SRCC ||
  ||HB![0]_CC || K16/L16 || MRCC ||
  ||HB![6]_CC || L15/L14 || MRCC ||
  ||HB![17]_CC || A16/B16 || SRCC ||


== MGTs ==
The FMC DP![0:7] pins are connected directly to Virtex-6 GTX transceiver dedicated pins. As required by the FMC spec, the WARP v3 board does not include any AC-coupling caps for MGT traces. The FMC module must include these in its MGT circuit.

The mapping of FMC DP![0:7] to FPGA GTX is listed below.
  ||= FMC DP =||= GTX LOC =||= GTX Tx+/Tx- Pins =||= GTX Rx+/Rx- Pins =||
  || 0 || 116_1 || C3/C4 || E3/D4 ||
  || 1 || 116_3 || A3/A4 || B5/B6 ||
  || 2 || 116_2 || B1/B2 || D5/D6 ||
  || 3 || 116_0 || D1/D2 || G3/G4 ||
  || 4 || 115_2 || H1/H2 || K5/K6 ||
  || 5 || 115_0 || M1/M2 || N3/N4 || 
  || 6 || 115_1 || K1/K2 || L3/L4 ||
  || 7 || 115_3 || F1/F2 || J3/J4 ||

FMC modules which use MGTs must also supply the MGT reference clock running at whatever frequency is required by the module's MGT circuits. The FMC spec defines two MGT reference clocks, both of which are connected on WARP v3. The FMC and FPGA connections are listed below.
  ||= FMC GBTCLK =||= FPGA Buffer =||= FPGA Pin =||
  || GBTCLK0_M2C_P || MGTREFCLK0P_115 || P6 ||
  || GBTCLK0_M2C_N || MGTREFCLK0N_115 || P5 ||
  || GBTCLK1_M2C_P || MGTREFCLK0P_116 || H6 ||
  || GBTCLK1_M2C_N || MGTREFCLK0N_116 || H5 ||

As required by the spec, the MGT clock signals are AC-coupled on the WARP v3 board by 100nF series capacitors. 

The WARP v3 board provides sufficient power to utilize all 8 MGTs simultaneously at their maximum rated speed.

For details on the protocols and frequencies supported by the MGTs refer to the [http://www.xilinx.com/support/documentation/user_guides/ug366.pdf Virtex-6 GTX Transceiver User Guide].

== JTAG == 
The FMC spec provides dedicated JTAG pins for routing a JTAG chain from the carrier card through ICs on the FMC module. On WARP v3 this JTAG chain operates at 3.3v. The only IC on this chain is the configuration CPLD. The chain is driven by a standard 14-pin JTAG header at J17 (back side).

If no FMC module is mounted a shunt must be mounted at J7 to complete the JTAG chain for access to the CPLD. The shunt should be removed when a JTAG-equipped FMC module is connected.

The FPGA JTAG interface is separate from the FMC/CPLD chain.

== Supported FMC Modules ==
The WARP v3 FMC implementation is designed to support FMC-compliant modules compatible with the voltage, I/O and clock connections listed above. Any module known to work on the Xilinx ML605 should work on WARP v3. As we test various third-party modules we will update this section.

If you're concerned about compatibility with a third-party module, please share this page with the module designer. The details above should be enough to confirm compatibility with our FMC implementation.

----

== FPGA Connections ==
The UCF snippet below lists the FPGA pins connected to the FMC slot.

{{{
#!sh
#####################################
###FMC HPC Connector
#Control
NET "FMC_CLK_DIR" LOC = "M23" | IOSTANDARD = "LVCMOS25";
NET "FMC_PRSNT_M2C" LOC = "H30" | IOSTANDARD = "LVCMOS25";
NET "FMC_I2C_SCL" LOC = "F23" | IOSTANDARD = "LVCMOS25";
NET "FMC_I2C_SDA" LOC = "F24" | IOSTANDARD = "LVCMOS25";

#Clocks
NET "FMC_CLK0_M2C_N" LOC = "K23" | IOSTANDARD = "LVDS_25" | DIFF_TERM = "TRUE";
NET "FMC_CLK0_M2C_P" LOC = "K24" | IOSTANDARD = "LVDS_25" | DIFF_TERM = "TRUE";
NET "FMC_CLK1_M2C_N" LOC = "M22" | IOSTANDARD = "LVDS_25" | DIFF_TERM = "TRUE";
NET "FMC_CLK1_M2C_P" LOC = "L23" | IOSTANDARD = "LVDS_25" | DIFF_TERM = "TRUE";

#I/O Bank HA
NET "FMC_HA00_CC_N" LOC = "B28" | IOSTANDARD = "LVCMOS25";
NET "FMC_HA00_CC_P" LOC = "C28" | IOSTANDARD = "LVCMOS25";
NET "FMC_HA01_CC_N" LOC = "D29" | IOSTANDARD = "LVCMOS25";
NET "FMC_HA01_CC_P" LOC = "C29" | IOSTANDARD = "LVCMOS25";
NET "FMC_HA02_N" LOC = "E27" | IOSTANDARD = "LVCMOS25";
NET "FMC_HA02_P" LOC = "D27" | IOSTANDARD = "LVCMOS25";
NET "FMC_HA03_N" LOC = "A31" | IOSTANDARD = "LVCMOS25";
NET "FMC_HA03_P" LOC = "B31" | IOSTANDARD = "LVCMOS25";
NET "FMC_HA04_N" LOC = "E28" | IOSTANDARD = "LVCMOS25";
NET "FMC_HA04_P" LOC = "F28" | IOSTANDARD = "LVCMOS25";
NET "FMC_HA05_N" LOC = "B30" | IOSTANDARD = "LVCMOS25";
NET "FMC_HA05_P" LOC = "A30" | IOSTANDARD = "LVCMOS25";
NET "FMC_HA06_N" LOC = "G28" | IOSTANDARD = "LVCMOS25";
NET "FMC_HA06_P" LOC = "H27" | IOSTANDARD = "LVCMOS25";
NET "FMC_HA07_N" LOC = "A26" | IOSTANDARD = "LVCMOS25";
NET "FMC_HA07_P" LOC = "B26" | IOSTANDARD = "LVCMOS25";
NET "FMC_HA08_N" LOC = "A25" | IOSTANDARD = "LVCMOS25";
NET "FMC_HA08_P" LOC = "B25" | IOSTANDARD = "LVCMOS25";
NET "FMC_HA09_N" LOC = "D26" | IOSTANDARD = "LVCMOS25";
NET "FMC_HA09_P" LOC = "D25" | IOSTANDARD = "LVCMOS25";
NET "FMC_HA10_N" LOC = "D30" | IOSTANDARD = "LVCMOS25";
NET "FMC_HA10_P" LOC = "C30" | IOSTANDARD = "LVCMOS25";
NET "FMC_HA11_N" LOC = "C25" | IOSTANDARD = "LVCMOS25";
NET "FMC_HA11_P" LOC = "C24" | IOSTANDARD = "LVCMOS25";
NET "FMC_HA12_N" LOC = "D22" | IOSTANDARD = "LVCMOS25";
NET "FMC_HA12_P" LOC = "C22" | IOSTANDARD = "LVCMOS25";
NET "FMC_HA13_N" LOC = "G27" | IOSTANDARD = "LVCMOS25";
NET "FMC_HA13_P" LOC = "G26" | IOSTANDARD = "LVCMOS25";
NET "FMC_HA14_N" LOC = "A19" | IOSTANDARD = "LVCMOS25";
NET "FMC_HA14_P" LOC = "A18" | IOSTANDARD = "LVCMOS25";
NET "FMC_HA15_N" LOC = "L21" | IOSTANDARD = "LVCMOS25";
NET "FMC_HA15_P" LOC = "L20" | IOSTANDARD = "LVCMOS25";
NET "FMC_HA16_N" LOC = "C27" | IOSTANDARD = "LVCMOS25";
NET "FMC_HA16_P" LOC = "B27" | IOSTANDARD = "LVCMOS25";
NET "FMC_HA17_CC_N" LOC = "G25" | IOSTANDARD = "LVCMOS25";
NET "FMC_HA17_CC_P" LOC = "F25" | IOSTANDARD = "LVCMOS25";
NET "FMC_HA18_N" LOC = "F26" | IOSTANDARD = "LVCMOS25";
NET "FMC_HA18_P" LOC = "E26" | IOSTANDARD = "LVCMOS25";
NET "FMC_HA19_N" LOC = "K22" | IOSTANDARD = "LVCMOS25";
NET "FMC_HA19_P" LOC = "K21" | IOSTANDARD = "LVCMOS25";
NET "FMC_HA20_N" LOC = "E24" | IOSTANDARD = "LVCMOS25";
NET "FMC_HA20_P" LOC = "D24" | IOSTANDARD = "LVCMOS25";
NET "FMC_HA21_N" LOC = "A29" | IOSTANDARD = "LVCMOS25";
NET "FMC_HA21_P" LOC = "A28" | IOSTANDARD = "LVCMOS25";
NET "FMC_HA22_N" LOC = "J22" | IOSTANDARD = "LVCMOS25";
NET "FMC_HA22_P" LOC = "H22" | IOSTANDARD = "LVCMOS25";
NET "FMC_HA23_N" LOC = "C18" | IOSTANDARD = "LVCMOS25";
NET "FMC_HA23_P" LOC = "B18" | IOSTANDARD = "LVCMOS25";

#I/O Bank HB
NET "FMC_HB00_CC_N" LOC = "L16" | IOSTANDARD = "LVCMOS25";
NET "FMC_HB00_CC_P" LOC = "K16" | IOSTANDARD = "LVCMOS25";
NET "FMC_HB01_N" LOC = "M17" | IOSTANDARD = "LVCMOS25";
NET "FMC_HB01_P" LOC = "M18" | IOSTANDARD = "LVCMOS25";
NET "FMC_HB02_N" LOC = "J19" | IOSTANDARD = "LVCMOS25";
NET "FMC_HB02_P" LOC = "K19" | IOSTANDARD = "LVCMOS25";
NET "FMC_HB03_N" LOC = "D17" | IOSTANDARD = "LVCMOS25";
NET "FMC_HB03_P" LOC = "E18" | IOSTANDARD = "LVCMOS25";
NET "FMC_HB04_N" LOC = "J16" | IOSTANDARD = "LVCMOS25";
NET "FMC_HB04_P" LOC = "J17" | IOSTANDARD = "LVCMOS25";
NET "FMC_HB05_N" LOC = "H18" | IOSTANDARD = "LVCMOS25";
NET "FMC_HB05_P" LOC = "G18" | IOSTANDARD = "LVCMOS25";
NET "FMC_HB06_CC_N" LOC = "L14" | IOSTANDARD = "LVCMOS25";
NET "FMC_HB06_CC_P" LOC = "L15" | IOSTANDARD = "LVCMOS25";
NET "FMC_HB07_N" LOC = "L18" | IOSTANDARD = "LVCMOS25";
NET "FMC_HB07_P" LOC = "L19" | IOSTANDARD = "LVCMOS25";
NET "FMC_HB08_N" LOC = "D16" | IOSTANDARD = "LVCMOS25";
NET "FMC_HB08_P" LOC = "E16" | IOSTANDARD = "LVCMOS25";
NET "FMC_HB09_N" LOC = "G17" | IOSTANDARD = "LVCMOS25";
NET "FMC_HB09_P" LOC = "H17" | IOSTANDARD = "LVCMOS25";
NET "FMC_HB10_N" LOC = "B17" | IOSTANDARD = "LVCMOS25";
NET "FMC_HB10_P" LOC = "C17" | IOSTANDARD = "LVCMOS25";
NET "FMC_HB11_N" LOC = "E17" | IOSTANDARD = "LVCMOS25";
NET "FMC_HB11_P" LOC = "F18" | IOSTANDARD = "LVCMOS25";
NET "FMC_HB12_N" LOC = "G16" | IOSTANDARD = "LVCMOS25";
NET "FMC_HB12_P" LOC = "F16" | IOSTANDARD = "LVCMOS25";
NET "FMC_HB13_N" LOC = "B15" | IOSTANDARD = "LVCMOS25";
NET "FMC_HB13_P" LOC = "A15" | IOSTANDARD = "LVCMOS25";
NET "FMC_HB14_N" LOC = "F15" | IOSTANDARD = "LVCMOS25";
NET "FMC_HB14_P" LOC = "G15" | IOSTANDARD = "LVCMOS25";
NET "FMC_HB15_N" LOC = "C15" | IOSTANDARD = "LVCMOS25";
NET "FMC_HB15_P" LOC = "D15" | IOSTANDARD = "LVCMOS25";
NET "FMC_HB16_N" LOC = "M15" | IOSTANDARD = "LVCMOS25";
NET "FMC_HB16_P" LOC = "M16" | IOSTANDARD = "LVCMOS25";
NET "FMC_HB17_CC_N" LOC = "B16" | IOSTANDARD = "LVCMOS25";
NET "FMC_HB17_CC_P" LOC = "A16" | IOSTANDARD = "LVCMOS25";
NET "FMC_HB18_N" LOC = "J15" | IOSTANDARD = "LVCMOS25";
NET "FMC_HB18_P" LOC = "H15" | IOSTANDARD = "LVCMOS25";
NET "FMC_HB19_N" LOC = "K17" | IOSTANDARD = "LVCMOS25";
NET "FMC_HB19_P" LOC = "K18" | IOSTANDARD = "LVCMOS25";

#I/O Bank LA
NET "FMC_LA00_CC_N" LOC = "G20" | IOSTANDARD = "LVCMOS25";
NET "FMC_LA00_CC_P" LOC = "F21" | IOSTANDARD = "LVCMOS25";
NET "FMC_LA01_CC_N" LOC = "C19" | IOSTANDARD = "LVCMOS25";
NET "FMC_LA01_CC_P" LOC = "B20" | IOSTANDARD = "LVCMOS25";
NET "FMC_LA02_N" LOC = "E23" | IOSTANDARD = "LVCMOS25";
NET "FMC_LA02_P" LOC = "E22" | IOSTANDARD = "LVCMOS25";
NET "FMC_LA03_N" LOC = "C23" | IOSTANDARD = "LVCMOS25";
NET "FMC_LA03_P" LOC = "B23" | IOSTANDARD = "LVCMOS25";
NET "FMC_LA04_N" LOC = "D19" | IOSTANDARD = "LVCMOS25";
NET "FMC_LA04_P" LOC = "E19" | IOSTANDARD = "LVCMOS25";
NET "FMC_LA05_N" LOC = "E21" | IOSTANDARD = "LVCMOS25";
NET "FMC_LA05_P" LOC = "D21" | IOSTANDARD = "LVCMOS25";
NET "FMC_LA06_N" LOC = "G22" | IOSTANDARD = "LVCMOS25";
NET "FMC_LA06_P" LOC = "G21" | IOSTANDARD = "LVCMOS25";
NET "FMC_LA07_N" LOC = "F20" | IOSTANDARD = "LVCMOS25";
NET "FMC_LA07_P" LOC = "F19" | IOSTANDARD = "LVCMOS25";
NET "FMC_LA08_N" LOC = "A24" | IOSTANDARD = "LVCMOS25";
NET "FMC_LA08_P" LOC = "A23" | IOSTANDARD = "LVCMOS25";
NET "FMC_LA09_N" LOC = "H20" | IOSTANDARD = "LVCMOS25";
NET "FMC_LA09_P" LOC = "H19" | IOSTANDARD = "LVCMOS25";
NET "FMC_LA10_N" LOC = "B22" | IOSTANDARD = "LVCMOS25";
NET "FMC_LA10_P" LOC = "B21" | IOSTANDARD = "LVCMOS25";
NET "FMC_LA11_N" LOC = "D20" | IOSTANDARD = "LVCMOS25";
NET "FMC_LA11_P" LOC = "C20" | IOSTANDARD = "LVCMOS25";
NET "FMC_LA12_N" LOC = "A21" | IOSTANDARD = "LVCMOS25";
NET "FMC_LA12_P" LOC = "A20" | IOSTANDARD = "LVCMOS25";
NET "FMC_LA13_N" LOC = "J21" | IOSTANDARD = "LVCMOS25";
NET "FMC_LA13_P" LOC = "J20" | IOSTANDARD = "LVCMOS25";
NET "FMC_LA14_N" LOC = "J14" | IOSTANDARD = "LVCMOS25";
NET "FMC_LA14_P" LOC = "K14" | IOSTANDARD = "LVCMOS25";
NET "FMC_LA15_N" LOC = "H14" | IOSTANDARD = "LVCMOS25";
NET "FMC_LA15_P" LOC = "G13" | IOSTANDARD = "LVCMOS25";
NET "FMC_LA16_N" LOC = "H13" | IOSTANDARD = "LVCMOS25";
NET "FMC_LA16_P" LOC = "G12" | IOSTANDARD = "LVCMOS25";
NET "FMC_LA17_CC_N" LOC = "M13" | IOSTANDARD = "LVCMOS25";
NET "FMC_LA17_CC_P" LOC = "L13" | IOSTANDARD = "LVCMOS25";
NET "FMC_LA18_CC_N" LOC = "M11" | IOSTANDARD = "LVCMOS25";
NET "FMC_LA18_CC_P" LOC = "M12" | IOSTANDARD = "LVCMOS25";
NET "FMC_LA19_N" LOC = "E14" | IOSTANDARD = "LVCMOS25";
NET "FMC_LA19_P" LOC = "F14" | IOSTANDARD = "LVCMOS25";
NET "FMC_LA20_N" LOC = "J12" | IOSTANDARD = "LVCMOS25";
NET "FMC_LA20_P" LOC = "H12" | IOSTANDARD = "LVCMOS25";
NET "FMC_LA21_N" LOC = "B13" | IOSTANDARD = "LVCMOS25";
NET "FMC_LA21_P" LOC = "B12" | IOSTANDARD = "LVCMOS25";
NET "FMC_LA22_N" LOC = "A14" | IOSTANDARD = "LVCMOS25";
NET "FMC_LA22_P" LOC = "A13" | IOSTANDARD = "LVCMOS25";
NET "FMC_LA23_N" LOC = "C14" | IOSTANDARD = "LVCMOS25";
NET "FMC_LA23_P" LOC = "D14" | IOSTANDARD = "LVCMOS25";
NET "FMC_LA24_N" LOC = "E11" | IOSTANDARD = "LVCMOS25";
NET "FMC_LA24_P" LOC = "D11" | IOSTANDARD = "LVCMOS25";
NET "FMC_LA25_N" LOC = "E12" | IOSTANDARD = "LVCMOS25";
NET "FMC_LA25_P" LOC = "D12" | IOSTANDARD = "LVCMOS25";
NET "FMC_LA26_N" LOC = "B11" | IOSTANDARD = "LVCMOS25";
NET "FMC_LA26_P" LOC = "A11" | IOSTANDARD = "LVCMOS25";
NET "FMC_LA27_N" LOC = "C12" | IOSTANDARD = "LVCMOS25";
NET "FMC_LA27_P" LOC = "C13" | IOSTANDARD = "LVCMOS25";
NET "FMC_LA28_N" LOC = "F13" | IOSTANDARD = "LVCMOS25";
NET "FMC_LA28_P" LOC = "E13" | IOSTANDARD = "LVCMOS25";
NET "FMC_LA29_N" LOC = "J10" | IOSTANDARD = "LVCMOS25";
NET "FMC_LA29_P" LOC = "J11" | IOSTANDARD = "LVCMOS25";
NET "FMC_LA30_N" LOC = "G10" | IOSTANDARD = "LVCMOS25";
NET "FMC_LA30_P" LOC = "H10" | IOSTANDARD = "LVCMOS25";
NET "FMC_LA31_N" LOC = "F11" | IOSTANDARD = "LVCMOS25";
NET "FMC_LA31_P" LOC = "G11" | IOSTANDARD = "LVCMOS25";
NET "FMC_LA32_N" LOC = "L11" | IOSTANDARD = "LVCMOS25";
NET "FMC_LA32_P" LOC = "K11" | IOSTANDARD = "LVCMOS25";
NET "FMC_LA33_N" LOC = "K12" | IOSTANDARD = "LVCMOS25";
NET "FMC_LA33_P" LOC = "K13" | IOSTANDARD = "LVCMOS25";

#MGTs (Tx=C2M=FPGA Ouput, Rx=M2C=FPGA Input)
NET "FMC_MGTCLK_AC_0_N" LOC = "P5";
NET "FMC_MGTCLK_AC_0_P" LOC = "P6";
NET "FMC_MGTCLK_AC_1_N" LOC = "H5";
NET "FMC_MGTCLK_AC_1_P" LOC = "H6";

NET "MGT_115_0_RX_N" LOC = "N4"; #FMC DP5
NET "MGT_115_0_RX_P" LOC = "N3";
NET "MGT_115_0_TX_N" LOC = "M2";
NET "MGT_115_0_TX_P" LOC = "M1";
NET "MGT_115_1_RX_N" LOC = "L4"; #FMC DP6
NET "MGT_115_1_RX_P" LOC = "L3";
NET "MGT_115_1_TX_N" LOC = "K2";
NET "MGT_115_1_TX_P" LOC = "K1";
NET "MGT_115_2_RX_N" LOC = "K6"; #FMC DP4
NET "MGT_115_2_RX_P" LOC = "K5";
NET "MGT_115_2_TX_N" LOC = "H2";
NET "MGT_115_2_TX_P" LOC = "H1";
NET "MGT_115_3_RX_N" LOC = "J4"; #FMC DP7
NET "MGT_115_3_RX_P" LOC = "J3";
NET "MGT_115_3_TX_N" LOC = "F2";
NET "MGT_115_3_TX_P" LOC = "F1";
NET "MGT_116_0_RX_N" LOC = "G4"; #FMC DP3
NET "MGT_116_0_RX_P" LOC = "G3";
NET "MGT_116_0_TX_N" LOC = "D2";
NET "MGT_116_0_TX_P" LOC = "D1";
NET "MGT_116_1_RX_N" LOC = "E4"; #FMC DP0
NET "MGT_116_1_RX_P" LOC = "E3";
NET "MGT_116_1_TX_N" LOC = "C4";
NET "MGT_116_1_TX_P" LOC = "C3";
NET "MGT_116_2_RX_N" LOC = "D6"; #FMC DP2
NET "MGT_116_2_RX_P" LOC = "D5";
NET "MGT_116_2_TX_N" LOC = "B2";
NET "MGT_116_2_TX_P" LOC = "B1";
NET "MGT_116_3_RX_N" LOC = "B6"; #FMC DP1
NET "MGT_116_3_RX_P" LOC = "B5";
NET "MGT_116_3_TX_N" LOC = "A4";
NET "MGT_116_3_TX_P" LOC = "A3";
#####################################
}}}