Changes between Initial Version and Version 1 of HardwareUsersGuides/WARPv3/FPGAConfig

Timestamp:

Jul 28, 2012, 7:18:52 PM (12 years ago)

Author:

murphpo

Comment:

--

HardwareUsersGuides/WARPv3/FPGAConfig

@@ +1 @@
+[[TracNav(HardwareUsersGuides/WARPv3/TOC)]]
+== WARP v3 User Guide: FPGA Configuration ==
+By default the FPGA is a "blank slate". The FPGA configuration is volatile and must be re-downloaded every time power is cycled. The WARP v3 board provides three FPGA configuration methods: JTAG, SD card and SPI flash.
+
+''config blk diagram here''
+
+----
+== JTAG ==
+The Xilinx FPGA includes dedicated JTAG pins for in-system configuration and debug. This JTAG interface is routed to a 14-pin connector (J14) on WARP v3. Accessing the JTAG interface requires an external JTAG programming cable.  The connector and pinout of J14 complies with the requirements of the Xilinx Platform configuration cables.
+
+The JTAG configuration interface is always enabled and can be used independent of the SD/SPI flash methods described below.
+
+Any JTAG cable supported by Xilinx iMPACT should work. We have tested the JTAG interface with these cables:
+
+ * [https://www.digilentinc.com/Products/Detail.cfm?Prod=JTAG-HS1 Digilent HS1 JTAG Programming Cable]
+ * [http://www.digilentinc.com/Products/Detail.cfm?Prod=XUP-USB-JTAG Digilent USB-JTAG Programming Cable]
+ * [http://www.xilinx.com/products/boards-and-kits/HW-USB-II-G.htm Xilinx Platform Cable USB II]
+
+The JTAG chain connected to J14 requires 2.5v I/O. The Virtex-6 FPGA is the only device on this chain. There is a second JTAG chain on the WARP v3 board which operates at 3.3v. This chain connects to the FMC JTAG pins and the configuration PLD JTAG interface.
+
+----
+== SD Card ==
+WARP v3 includes an SD card slot for loading FPGA configurations from removable flash cards. An SD card can contain up to 8 bitstreams, with the active bitstream selected at configuration time via a DIP switch. After loading a bitstream from an SD card, the card can be removed without interrupting operation of the newly-loaded FPGA design. This is very useful for rapidly configuring multiple nodes using a single SD card.
+
+=== Selecting SD Card for Configuration ===
+To select the SD card as the configuration source, set position 1 of DIP SW SW2 to 0. 
+'''picture here'''
+
+The WARP v3 configuration PLD implements the following behavior in this mode:
+ * The PLD acts as an SPI master to access the SD card and a master for the FPGA slave serial configuration mode.
+ * The SD card will be reset and switched to SPI mode on power up and whenever a new card is inserted.
+ * A configuration cycle will initiate on  power up, when a new SD card is inserted or when you press the '''RECONFIG''' push button (PB4).
+ * During configuration the '''STAT''' LED (D17) is driven by the FPGA CCLK signal and will appear to be partially illuminated as the bitstream is loaded. If configuration succeeds the LED will illuminate fully.
+ * The '''ERR''' LED (D18) will illuminate if an error is detected during configuration. The most likely cause of errors is an invalid FPGA configuration bitstream stored in the SPI flash.
+
+Positions 2-4 of the DIP switch select which file on the SD card is used for configuration.
+'''picture here'''
+
+
+=== Preparing an FPGA Bitstream ===
+When configuring the FPGA via slave serial mode the configuration startup clock must be CCLK. The default XPS bitgen.ut specifies the JTAG clock, along with other options that are unnecessary for configuration from the SD card. Change the XPS bitgen.ut to:
+{{{
+-g StartupClk:Cclk
+}}}
+
+The SD card configuration mode uses the binary bitstream format (.bin files). To automatically generate a .bin file:
+ * ISE: open the Generate Programming File properties and check Create Binary Configuration File
+ * XPS: edit Project -> bitgen.ut, add a line:
+{{{
+-g Binary:Yes
+}}}
+
+To convert an existing .bit file to .bin:
+ * Open a Xilinx command prompt
+ * Run:
+{{{
+promgen -u 0 yourFile.bit -p bin -spi
+}}}
+
+=== Programming an SD Card ===
+We recommend using a standard SD card (not SDHC, SDXC, etc.) with a capacity <=2GB.
+
+Every WARP v3 kit ships with a pre-tested SD card. These SD cards are divided into two partitions. The first is a 32MB FAT16 partition, occupying the lowest sectors of the SD card. The second partition occupies the rest of the card and is unformatted. FPGA configuration files are written to this unformatted space as raw binary files.
+
+When you mount the card on your PC your OS should recognize and mount the small FAT partition. Because the WARP v3 board will ignore this partition, you can use it if desired. We suggest storing a text file there describing which designs are written to the SD card's configuration slots.
+
+|| [[Image(wiki:HardwareUsersGuides/WARPv3/files:important.png,valign=middle,nolink)]] || '''WARNING:''' the tools for writing binary files to arbitrary locations on the SD card are also capable of overwriting critical areas of your computer's hard drive. '''Always''' verify the output device descriptor before running these tools. ||
+
+The default WARP v3 CPLD design loads configuration files from the SD card starting at an offset of 64MB. Up to 8 configuration files can be stored per card, with each file separated by 16MB.
+
+We use the open-source dd tool to write configuration files to SD cards. dd is available for OS X, Linux and Windows (and probably other OSs). Each call to dd copies one configuration file. There are four arguments:
+{{{
+dd bs=512 seek=BaseAddr if=someFile.bin of=sdCardDevice
+}}}
+ * bs: Block size, always 512 for SD cards
+ * if: input file (your .bin file)
+ * of: device descriptor for SD card (OS specific; see below)
+ * seek: Staring address for the output file, in units of block size. Use (131072 + slotNum*32768) for standard WARP v3 config design:
+  * File 0: 131072
+  * File 1: 163840
+  * File 2: 196608
+  * File 3: 229376
+  * File 4: 262144
+  * File 5: 294912
+  * File 6: 327680
+  * File 7: 360448
+
+'''OS X'''[[BR]]
+ 1. Insert SD card
+ 1. Run {{{diskutil list}}} to find device descriptor for SD card. Use this in place of {{{/dev/diskX}}} below.
+ 1. Unmount ('''not''' eject) the drive using Disk Utility or this command:
+{{{
+diskutil unmountDisk /dev/diskX
+}}}
+
+For each configuration file you wish to write:
+ 1. Run:
+{{{
+dd bs=512 seek=N if=yourFile.bin of=/dev/diskX
+}}}
+ 2. See above for correct values of seek argument
+ 1. If successful, dd will report how many bytes were written and how long it took (usually ~10 seconds on our test machines).
+ 1. Some versions of OS X re-mount the FAT volume after each call to dd. Run {{{diskutil unmountDisk /dev/diskX}}} again to un-mount it.
+ 1. Repeat for additional config files if needed.
+
+'''Linux'''[[BR]]
+ * Find device descriptor
+ * same dd cmds as OS X
+
+'''Windows'''[[BR]]
+
+
+----
+== SPI Flash ==
+The WARP v3 board includes a 128Mb SPI flash device (Numonyx M25P128). This device can be used to configure the FPGA at power-up without an external JTAG cable or SD card. Configuration from SPI flash uses the Virtex-6 Master SPI mode.
+
+=== Selecting SPI Flash for Configuration ===
+To select the SPI Flash as the configuration source, set position 1 of DIP SW SW2 to 1.
+''photo here''
+
+The WARP v3 configuration PLD implements the following behavior in this mode:
+ * The FPGA and flash SPI interfaces are tied together with the FPGA acting as SPI master.
+ * The PLD initiates a Master SPI configuration cycle at power up.
+ * The '''RECONFIG''' push button (PB4) is tied to the FPGA INIT_B signal. Pushing the button initiates an FPGA configuration cycle.
+ * During configuration the '''STAT''' LED (D17) is driven by the FPGA CCLK signal and will appear to be partially illuminated as the bitstream is loaded. If configuration succeeds the LED will illuminate fully.
+ * The '''ERR''' LED (D18) will illuminate if an error is detected during configuration. The most likely cause of errors is an invalid FPGA configuration bitstream stored in the SPI flash.
+
+=== Programming the SPI Flash ===
+The SPI flash is programmed via iMPACT. Programming the SPI flash requires two steps- generating the PROM file and writing the PROM file to the flash.
+
+The PROM programming file (.mcs file) can be generated via the iMPACT GUI or with the promgen command.
+
+'''To generate the PROM programming file via the iMPACT GUI:'''
+ 1. Open iMPACT and start the '''Create PROM File''' flow
+ 1. In the PROM File Formatter window:
+  1. Set '''Storage Target''' to '''SPI Flash -> Configure Single FPGA'''
+  1. Click the first green arrow
+  1. Set '''Storage Device''' to '''128M'''
+  1. Click '''Add Storage Device''', then click the second green arrow
+  1. Change the '''Output File Name''' and '''Output File Location''' to your preferred path
+  1. Set '''File Format''' to '''MCS''' and '''Add Non-Configuration Data Files''' to '''No'''
+  1. Click '''OK'''
+ 1. Click '''OK''' in the Add Device dialog box
+ 1. Select your desired FPGA configuration .bit file
+ 1. Click '''No''' when prompted to add another device file, then click '''OK''' to continue
+ 1. Right-click in the iMPACT window and choose '''Generate File'''
+
+'''To generate the PROM programming file via promgen:'''
+ 1. Launch a Xilinx command prompt
+ 1. Navigate to the folder with your .bit file
+ 1. Run:
+{{{
+promgen -spi -p mcs -c FF -s 131072 -u 0 <your .bit file name> -o <new .mcs file name>
+}}}
+
+'''To write the .mcs file to the SPI flash:'''
+ 1. Connect a programming cable to the FPGA JTAG connector (J14)
+ 1. Run iMPACT (if not already open) and start the '''Boundary Scan''' flow
+ 1. Right-click and choose '''Initialize Chain'''
+ 1. Click '''OK''' in the Device Programming Properties window
+ 1. Right-click on the FPGA icon and select '''Add BPI/SPI Flash'''
+ 1. Select your .mcs file
+ 1. The Select Attached SPI/BPI window will show. Choose '''SPI PROM''' model '''M25P128''', data width 1.
+ 1. Right-click on the Flash icon (''not'' the FPGA icon) and choose '''Program'''
+ 1. Confirm '''Design-Specific Erase Before Programming''' is checked
+ 1. Optionally un-check '''Verify'''; verification increases the programming time, and we've never seen a verification error
+ 1. Click '''OK'''
+
+iMPACT will now begin writing your .mcs file to the SPI flash. This process is slow, typically requiring 3+ minutes. Watch the iMPACT GUI and console for status and error messages.
+
+When the programming process completes the FPGA will initiate a configuration cycle from the flash. You will see the green '''STAT''' LED glow at half intensity as the FPGA reads the configuration file. The LED will illuminate fully when configuration completes.
+
+=== Configuration Clock Frequency ===
+The FPGA uses Master SPI mode when loading a bitstream from the SPI flash. In this mode the FPGA generates the configuration clock signal and drives it to the CCLK pin. The CCLK pin is routed to the SPI serial clock input. A faster CCLK will result in a faster configuration process.
+
+The CCLK frequency is specified in the .bit file and is preserved when generating the .mcs file (as described above). You can change the CCLK frequency via the {{{-g ConfigRate}}} bitgen option. We have successfully tested CCLK frequencies up to 33MHz. Higher frequencies will sometimes work. However the FPGA-generated CCLK frequency is specified as ±55%, so higher nominal frequencies may violate the SPI flash max frequency of 54MHz.
+
+To set the CCLK frequency to 33MHz:
+ * ISE: open the Generate Programming File properties and change Configuration Options -> ConfigRate to 33.
+ * XPS: edit Project -> bitgen.ut, add a line:
+{{{
+-g ConfigRate:33
+}}}
+
+You will need to re-generate the .mcs file and re-program the SPI flash if you change the CCLK frequency.
+
+----
+
+== Configuration PLD ==
+The WARP v3 board uses a Xilinx Coolrunner-II PLD to manage the SD card and SPI flash configuration interfaces. This PLD is pre-configured with a standard design which supports both interfaces and implements the behaviors described above. The PLD retains its configuration while powered down. Most users will never need to modify the PLD design.
+
+To load a new PLD configuration use the JTAG interface routed to J17. This JTAG chain also includes the dedicated JTAG pins for the FMC header. Mount a shunt on header J7 to bypass the FMC JTAG interface if no FMC module is mounted or the mounted FMC module does not use JTAG. This JTAG chain uses 3.3v I/O and has been tested with the same programming cables listed above.
+
+The source code for the default PLD design is available in [source:somePLDsourcePath the repository]. The SD card configuration mode is based on the excellent spi_boot project from OpenCores. Please see the [source:readme readme file] in the repository for details on licensing and our (thankfully minor) changes to the original spi_boot code.
+
+=== CPLD - FPGA I/O ===
+In addition to the FPGA configuration pins, there are 11 CPLD pins tied to general purpose FPGA I/O pins. The default CPLD design does not use these signals. They are available for custom designs requiring post-configuration access to the SPI flash or SD card, or any other configuration-related customizations.
+
+The FPGA and CPLD pin assignments are listed below.
+
+||= FPGA Pin =||= CPLD Pin =||= Net Name =||= Config Use =||= FPGA IO After Config =||
+|| R8 || 96 || FPGA_DONE || DONE || No ||
+|| P8 || 95 || FPGA_INIT || INIT_B || No ||
+|| L8 || 94 || FPGA_PROG || PROG_B || No ||
+|| H8 || 76 || FPGA_DIN || SPI MISO || No ||
+|| K8 || 78 || FPGA_CCLK || CCLK || No ||
+|| AA24 || 99 || FPGA_MOSI || SPI MOSI || Yes ||
+|| Y24 || 97 || FPGA_FCS || SPI Chip Select || Yes ||
+|| J25 || 85 || CPLD_GPIO0 || - || Yes ||
+|| N24 || 86 || CPLD_GPIO1 || - || Yes ||
+|| N23 || 87 || CPLD_GPIO2 || - || Yes ||
+|| P24 || 89 || CPLD_GPIO3 || - || Yes ||
+|| R24 || 90 || CPLD_GPIO4 || - || Yes ||
+|| H25 || 82 || CPLD_GPIO5 || - || Yes ||
+|| L24 || 81 || CPLD_GPIO6 || - || Yes ||
+|| H24 || 80 || CPLD_GPIO7 || - || Yes ||
+|| J24 || 79 || CPLD_GPIO8 || - || Yes ||
+|| T24 || 92 || CPLD_GPIO9 || - || Yes ||
+|| T23 || 91 || CPLD_GPIO10 || - || Yes ||
+
+
+----
+== Related Resources ==
+ * [http://www.xilinx.com/support/documentation/user_guides/ug360.pdf Virtex-6 Configuration User Guide]
+ * [http://opencores.org/project,spi_boot OpenCores SD/MMC Bootloader Project]
+ * [http://www.chrysocome.net/dd Windows port of dd]