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FPGAConfig

v7	v8
66	66	To load a new PLD configuration use the JTAG interface routed to J17. This JTAG chain also includes the dedicated JTAG pins for the FMC header. Mount a shunt on header J7 to bypass the FMC JTAG interface if no FMC module is mounted or the mounted FMC module does not use JTAG. This JTAG chain uses 3.3v I/O and has been tested with the same programming cables listed above.
67	67
68		The source code for the default PLD design is available in [source:~~somePLDsourcePath the repository]. The SD card configuration mode is based on the excellent spi_boot project from OpenCores. Please see the [source:readme~~ readme file] in the repository for details on licensing and our (thankfully minor) changes to the original spi_boot code.
	68	The source code for the default PLD design is available in [source:Hardware/WARP_v3/Rev1.1/Config_CPLD/src the repository]. The SD card configuration mode is based on [http://opencores.org/project,spi_boot Arnim Laeuger's spi_boot project] from OpenCores. Please see the [source:Hardware/WARP_v3/Rev1.1/Config_CPLD/Readme.txt readme file] in the repository for details on licensing and our (thankfully minor) changes to the original spi_boot code.
69	69
70	70	=== CPLD - FPGA I/O ===