Changes between Version 4 and Version 5 of HardwareUsersGuides/WARPv3/RF


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Timestamp:
Aug 12, 2012, 4:25:45 PM (12 years ago)
Author:
murphpo
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  • HardwareUsersGuides/WARPv3/RF

    v4 v5  
    11[[TracNav(HardwareUsersGuides/WARPv3/TOC)]]
    2 == WARP v3 User Guide: RF Interfaces ==
    3 '''Coming soon'''
     2= WARP v3 User Guide: RF Interfaces =
    43
    5 ----
     4The WARP v3 board integrates two identical RF interfaces. The basic structure of each interface is illustrated below.
    65
    7 == Tx DCO Calibration ==
     6[[Image(wiki:HardwareUsersGuides/WARPv3/files:w3_RF_blkDiag.png, nolink)]]
    87
    9 Each analog Tx I/Q path on WARP v3 may have small DC offset. This is caused by normal variations in component values and inherent offsets in the analog and RF ICs. It is important this DC offset is removed to avoid carrier leakage (LO leakage) in transmitted RF waveforms.
     8== AD9963 ADC/DAC ==
    109
    11 === Applying Tx DCO Calibration ===
     10The conversion between the analog I/Q and digital I/Q domains is handled by the Analog Devices AD9963 MxFE. The AD9963 integrates two 100MSps 12-bit ADCs, two 170MSps 12-bit DACs, interpolation and decimation filters and programmable analog gain and offset adjustments. Refer to the ADI [http://www.analog.com/static/imported-files/data_sheets/AD9961_9963.pdf AD9963 datasheet] for full specifications.
    1211
    13 Every node is calibrated during manufacturing, with the calibration values stored in the board's EEPROM. You should read and apply these calibration values in every custom design which uses the RF interfaces.
     12The AD9963 is very flexible and includes a register bank to control various functions on the chip. The registers are accessed via a dedicated SPI interface. We have designed the [wiki:/cores/w3_ad_controller w3_ad_controller] core to access the AD9963 registers via the SPI interface.
    1413
    15 The Tx DCO calibration values are stored at dedicated bytes in the EEPROM. See the [wiki:../EEPROM EEPROM page] for details.
     14The digital I/Q ports on the AD9963 operate at double data rate, with I/Q interleaved. We have designed the [wiki:/cores/w3_ad_bridge w3_ad_bridge] core to connect these DDR ports to separate internal I/Q busses in user designs.
    1615
    17 The WARP v3 design uses auxiliary DACs in the AD9963 to apply small DC offsets to the differential I/Q DAC outputs. The auxiliary DACs are configured via SPI. The [wiki:/cores/w3_ad_controller w3_ad_controller] driver provides functions for writing the DAC values from user code.
     16== MAX2829 Transceiver ==
    1817
    19 User designs should read Tx DCO calibration values from the EEPROM and update the AD9963 auxiliary DACs on every boot. The [wiki:/cores/radio_controller radio_controller] driver provides the function radio_controller_apply_TxDCO_calibration() implementing this process.
     18The WARP v3 RF interfaces use the Maxim MAX2829 transceiver to translate between baseband and RF. The MAX2829 implements both 2.4 and 5GHz Tx/Rx paths. For full specifications refer to the [http://datasheets.maxim-ic.com/en/ds/MAX2828-MAX2829.pdf MAX2829 datasheet].
    2019
     20The MAX2829 transceiver has a number of digital control lines and a dedicated SPI interface for internal register access. We have designed the [wiki:/cores/radio_controller radio_controller] core to manage these control interfaces in user designs.
    2121
    22 === Updating Tx DCO Calibration ===
    23 You may wish to occasionally re-run the Tx DCO calibration process to account for drift in component values with temperature and age. We provide a pre-built FPGA design which implements the Tx DCO calibration process. To use the design:
     22Each transceiver generates its own RF carrier signal, derived from a reference clock input. The reference clocks for both RF interfaces are driven by an AD9512 clock buffer (see [wiki:../Clocking for details]). The MAX2829 requires either a 20MHz or 40MHz reference clock. The AD9512 must be configured to divide its 80MHz input to generate the desired reference frequency.
    2423
    25  1. Terminate the RF interface to be calibrated into a 50 ohm load. The SMA terminators included with the WARP v3 kit are good for this. Alternately you can connect the RF interface to a spectrum analyzer to observe the Tx DCO calibration results.
    26  1. Connect a micro USB cable to the USB-UART interface, and connect a terminal emulator to the virtual serial port with baud rate 57600bps
    27  1. Download [export:warpv3_txdco_calibration.bit warpv3_txdco_calibration.bit]
    28  1. Configure the WARP v3 node using warpv3_txdco_calibration.bit
    29  1. A menu will be printed to the UART; press 1 or 2 to calibrate RF A or RF B
    30  1. The calibration process is automatic and executes in <1 minute
    31  1. When complete, the new calibration values will be recorded to the EEPROM
    32  1. The RF interface will now transmit a pure sinusoid at 2460MHz (8MHz baseband tone, center frequency of 2452MHz). You should observe a very low power tone at the center frequency, resulting from any residual Tx DCO. You can use the keyboard to further adjust the Tx DCO to check if the auto-calibration routine choose sub-optimal values. If you find values which show less energy at the center frequency, you can re-write the EEPROM by pressing {{{r}}}.
     24== Power Amplifier ==
    3325
    34 Repeat this process for the other RF interface if desired. Always ensure the SMA connector of the active interface is terminated into 50 ohms before running the calibration routine.
     26The WARP v3 design currently uses the Anadigics AWL6951 dual-band power amplifier. Every board is tested to ensure >20dBm output power at both 2.4 and 5GHz. Refer to the [http://www.anadigics.com/sites/default/files/datasheets/AWL6951_Rev_2.1.pdf AWL6951 datasheet] for full specifications.
     27
     28== RF Port ==
     29
     30Each RF interface is connected to a 50 ohm SMA jack. This connector is a standard polarity, standard thread SMA jack. The SMA jack should always be terminated into a 50 ohm load. The WARP v3 kit includes SMA terminators for each RF interface. Users must supply their own RF cables or antennas to suit their application.
     31
     32The maximum input power at the SMA connector should never exceed 0dBm, to avoid damage to the MAX2829 RF inputs.
     33
     34The performance of the MAX2829 RF inputs are specified for input powers below approximately -10dBm. To connect two WARP v3 kits via a coax cable, ensure there is at lest 40dB series attenuation.
     35