Changes between Version 7 and Version 8 of HardwareUsersGuides/WARPv3/RF


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Timestamp:
Aug 13, 2012, 12:05:19 AM (12 years ago)
Author:
murphpo
Comment:

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  • HardwareUsersGuides/WARPv3/RF

    v7 v8  
    5959
    6060The DLL parameters (M/N), ADC clock divider and mux selects are all configured via SPI register writes. The correct settings depend on the desired sampling rate, the Tx and Rx data rates at the FPGA and the AD9963 rate-change filter settings.
     61
     62The REF_CLK signal is generated by the sampling clock buffer on the WARP v3 board. This signal is derived from the 80MHz TCXO and can be divided by the clock buffer before being driven to the AD9963s. Refer to the [wiki:../Clocking#SamplingClock WARP v3 Clocking] page for more details.
    6163
    6264Some examples of valid combinations of clock sources, clock frequencies and filter settings are listed below. Many other valid combinations are possible. Note that the w3_ad_bridge and w3_ad_controller do not enforce valid combinations, as these cores do not know what clocks are connected in hardware. The user design must ensure correct settings.