wiki:OFDM/MIMO/Docs/ModelPorts

MIMO OFDM | Documentation? | OFDM Model Top-level Ports

Clocks

The entire MIMO OFDM model is driven by a single clock and has one top-level clock enable. The clock signal connected to splb_clk must be the same clock which drives the ADC/DACs on the radio daughtercards and the converter_clock_in port on the corresponding radio_bridge cores.

PortDefaultDirectionWidth
splb_clksys_clk_sInput1
splb_rstnet_gndInput1

PLB Slave Interface Ports

The model includes a standard PLB46 slave interface, automatically generated by the System Generator EDK Export flow. This interface is used to connect the OFDM core to an embedded PowerPC or Microblaze processor in the FPGA. This interface must be connected to a processor in order to use the OFDM core in hardware.

The ports all have prefix sl_ or plb_. These will be automatically connected to the host bus when the bus interface is connected in the EDK.

BRAM Interface Ports

The model includes a BRAM initiator interface, used to access the shared 64KB PLB_BRAM packet buffer. The packet buffer is not included in the OFDM design; it must be instantiated in the EDK project and connected to the OFDM core via these ports.

The BRAM ports are grouped into a BRAM_INITIATOR bus definition to facilitate their easy connection in the EDK's System Assembly View.

PortDefaultDirectionWidth
bram_addrBRAM_AddrOutput32
bram_datainBRAM_DinInput64
bram_doutBRAM_DoutOutput64
bram_resetBRAM_RstOutput1
bram_wenBRAM_WENOutput8

OFDM Core

The OFDM core uses dedicated top-level ports to interface with other peripheral cores. Some of these signals are connected to radio bridges, which route the signals off-chip to radio daughtercards. The rest connect to other custom cores for radio-specific PHY functions like AGC and packet detection.

PortDefaultDirectionWidthNotes
rx_anta_adciInput14I channel ADC input from antenna A
rx_anta_adcqInput14Q channel ADC input from antenna A
rx_antb_adciInput14I channel ADC input from antenna B
rx_antb_adcqInput14Q channel ADC input from antenna B
tx_anta_dac_iOutput16I channel DAC output for antenna A
tx_anta_dac_qOutput16Q channel DAC output for antenna A
tx_antb_dac_iOutput16I channel DAC output for antenna B
tx_antb_dac_qOutput16Q channel DAC output for antenna B
rssi_clk_outOutput1Clock for the RSSI ADC on every radio board; should be connected to corresponding port on each radio bridge
rssi_antaInput10Antenna A RSSI ADC value; should be connected to corresponding radio bridge output port
rssi_antbInput10Antenna B RSSI ADC value; should be connected to corresponding radio bridge output port
rx_int_badheaderOutput1Interrupt output signaling a received packet header failed CRC
rx_int_badpktOutput1Interrupt output signaling a received packet failed CRC
rx_int_goodpktOutput1Interrupt output signaling a received packet passed CRC and is ready for higher-layer processing
rx_int_goodheaderOutput1Interrupt output signaling a received packet's header was error-free; only asserts for packets with a payload beyond the header
rx_pktdetreset Output1Active-high output indicating that packet detection events should be ignored while the PHY is busy
rx_reset Input1Active-high global reset input; clears all internal state in the receiver model; does not clear register values
rx_anta_agc_doneInput1Status signal from AGC core for antenna A; asserts high when AGC has settled
rx_anta_gainbbInput5Baseband gain value in [0...63] chosen by AGC on antenna A. Only valid after rx_antb_agc_done asserts
rx_anta_gainrfInput2RF gain value in [1,2,3] chosen by AGC on antenna A. Only valid after rx_antb_agc_done asserts
rx_antb_agc_doneInput1Status signal from AGC core for antenna A; asserts high when AGC has settled
rx_antb_gainbbInput5Baseband gain value in [0...63] chosen by AGC on antenna B. Only valid after rx_antb_agc_done asserts
rx_antb_gainrfInput2RF gain value in [1,2,3] chosen by AGC on antenna B. Only valid after rx_antb_agc_done asserts
tx_resetInput1Active-high global reset input; clears all internal state in the transmitter model; does not clear register values
tx_starttransmit Input1Active-high trigger to begin transmission of a packet; usually tied to one of the radio controller's TxStart outputs
tx_pktdone Output1Active-high output indicating a packet transmission has finished

Debugging Ports

The core contains a number of top-level ports dedicated to debugging the design in hardware. These tend to change with each revision and can usually be identified as having "debug" in their names.

Last modified 10 years ago Last modified on Aug 29, 2009, 9:50:45 PM