wiki:OFDM/MIMO/Docs/ModelRegisters

MIMO OFDM | Documentation? | OFDM Model Register Map

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Register Map

The table below lists the registers in the MIMO OFDM transceiver. Each register is 32-bits wide, though not all registers use all 32 bits. The field names in each register link to their description below the table. The addresses specified here are relative to the base address of the OFDM pcore when instantiated in an EDK project.

An Excel spreadsheet of this register map is also available.

Reg Rx_ControlBits Rx_OFDM_SymbolCounts Rx_PktDet_Delay Rx_PktDet_LongCorr_Params Rx_PktDone_Reset Rx_pktByteNums Rx_pktDet_Tresholds TxRx_FFT_Scaling Rx_FreqOffFilt_B_KI Rx_FreqOffFilt_B_KP Rx_PhaseNoiseTrack_K Rx_PhaseNoiseTrack_Kalpha Rx_PhaseNoiseTrack_Kbeta Rx_PhaseNoiseTrack_Kgamma Rx_Constellation_Scaling Tx_PreambleScaling Tx_RandomPayload_ModulationSelt Tx_Pilots_Index1 Tx_Pilots_Index2 Tx_Pilots_Value1 Tx_Pilots_Value2 Tx_OFDM_SymCounts Tx_Start_Reset_Control Tx_ControlBits Rx_Gains Rx_BER_Errors Rx_BER_TotalBits Rx_packet_done Tx_PktDone
Dir RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RO RO RO RO RO
Addr 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70
31 RX_GLOBAL_RESET NUM_BASERATE_SYMS RESERVED CORR_THRESHOLD RESERVED PKT_BYTENUM_MODMASKS RESERVED RESERVED CFO_FILT_COEF_I CFO_FILT_COEF_P PHASE_TRACK_K PHASE_TRACK_KALPHA PHASE_TRACK_KBETA PHASE_TRACK_KGAMMA ANT_B_SCALING RESERVED RESERVED RESERVED RESERVED PILOT1_ANTB_VALUE PILOT2_ANTB_VALUE NUM_PYLD_SYMS RESERVED RESERVED RESERVED BER_ERRORS BER_TOTALBITS RESERVED RESERVED
30 RESERVED
29
28
27
26
25
24
23 PKT_BYTENUM_NUMBYTES_MSB
22
21 COARSE_CFO_CALC_DLY PILOT1_INDEX_2 PILOT2_INDEX_2
20
19 PKTDET_ENERGY_THRESH
18 SISO_ON_ANTB
17 SWITCHING_DIV_EN
16 SIMPLE_DYN_MOD_EN
15 RESERVED NUM_TRAINING_SYMS CORR_SET_TIMING PKT_BYTENUM_NUMBYTES_LSB ANT_A_SCALING PREAMBLE_SCALING RESERVED RESERVED PILOT1_ANTA_VALUE PILOT2_ANTA_VALUE NUM_BASERATE_SYMS
14 EQ_BYPASS_DIVISION RX_GAINS_ANTA_RF
13 USE_PILOT_ARCTAN
12 CFO_USE_LONGCORR SYMBOM_TIMING_OFFSET RX_GAINS_ANTA_BB
11 RESERVED PLBPKTBUF_RX_OFFSET RX_FFT_SCALING_0
10 CFO_USE_LTS
9 BYPASS_CARR_REC PLBPKTBUF_TX_OFFSET RX_FFT_SCALING_1
8 INT_PKT_DETECT TX_SISO_ANTB
7 EXT_PKT_DETECT RESERVED PKTDET_CORR_THRESH RX_FFT_SCALING_2 NUM_TRAINING_SYMS ANTB_PREAMBLE_SHIFT RESERVED
6 REQ_SHORT_CORR PKT_DET_DELAY RX_GAINS_ANTA_RF
5 REQ_TWO_LONG_CORR EN_BADPKT_INT TX_FFT_SCALING_0 PILOT1_INDEX_1 PILOT2_INDEX_1
4 RX_SISO_MODE EN_GOODPKT_INT RX_GAINS_ANTA_BB
3 RESERVED RESERVED TX_FFT_SCALING_1 EN_PILOT_SCRAMBLING
2 DYNAMC_PKT_LENGTHS TX_PKTDONE_RESET DISABLE_ANTB_PREAMBLE
1 REQ_LONG_CORR RST_BADPKT_INT TX_FFT_SCALING_2 RAND_PLD_MOD_SEL TX_START RESERVED RX_BADPKT_DONE
0 BER_RESET RST_GOODPKT_INT TX_RESET SISO_MODE RX_GOODPKT_DONE TX_PKT_DONE

Rx_ControlBits

Dir: Read/Write

Fields:

RX_GLOBAL_RESET

(Bit 31) Active high top-level reset signal for nearly all state registers in the Rx PHY.

SISO_ON_ANTB

(Bit 18) Use antenna B when in SISO mode; ignored when in MIMO mode.

SWITCHING_DIV_EN

(Bit 17) Enables switching diversity between antenna A and B in SISO mode; ingored when in MIMO mode. The Rx PHY chooses the antenna with the lower AGC-set gains per packet when enabled.

SIMPLE_DYN_MOD_EN

(Bit 16) Enables dynamic modulation support, which reads payload modulation information from the received header.

EQ_BYPASS_DIVISION

(Bit 14) Bypasses the complex divider in the equalizer, resulting in phase-only equalization. This is useful only when using BPSK or QPSK modulation schemes.

USE_PILOT_ARCTAN

(Bit 13) Enables the CORDIC arctangent calculation in the pilot phase estimator. This should be enabled for normal operation.

CFO_USE_LONGCORR

(Bit 12) Enables the use of the long correlator to control the timing of the carrier frequency offset estimation based on the long training symbols. This must be set to 1 for normal operation.

CFO_USE_LTS

(Bit 10) Enables carrier frequency offset estimation based on the preamble's long training symbols. Must be set to 1 for normal operation.

BYPASS_CARR_REC

(Bit 9) When set to 1, CFO correction is bypassed. This should only be used when driving two nodes from a common reference clock during PHY debugging.

INT_PKT_DETECT

(Bit 8) Enables the internal packet detection block. This should only be used when debugging the PHY over a wire when the external packet detector is not being used.

EXT_PKT_DETECT

(Bit 7) Enables external packet detection via the rx_extpktdet top-level port

REQ_SHORT_CORR

(Bit 6) Requires either internal or external packet detection in order to begin processing a packet. When disabled, the receiver will begin processing packets when trigged only by the long correlator.

REQ_TWO_LONG_CORR

(Bit 5) Requires two threshold crossings from the long correlator, spaced exactly 64 cycles apart. When enaled, this makes packet detection more robust at the cost of more false negative detections.

SISO_MODE

(Bit 4) Enables single-antenna (SISO) mode in the receiver. In this mode, only packets transmitted in SISO mode will be properly received.

DYN_PKT_LENGTHS

(Bit 2) Enables dynamic packet lengths. This should be 1 for normal operation. When disabled, the receiver assumes every packet is a fixed length. This is useful during PHY debugging and BER testing.

REQ_LONG_CORR

(Bit 1) Requires a threshold crossing in the long correlator for packet detection. This must be one for reliable operation.

BER_RESET

(Bit 0) When enabled, the BER calculation engine is held in reset. This should be 0 only during BER testing.


Rx_OFDM_SymbolCounts

Dir: Read/Write

Fields:

NUM_BASERATE_SYMS

(Bits 31:16 - UFix16_0) This integer sets the number of base rate symbols the receiver should process with each incoming packet. See the OFDM frame format documentation for more information.

NUM_TRAINING_SYMS

(Bits 15:0 - UFix16_0) This integer sets the number of training symbol periods at the receiver. This value corresponds to the number of OFDM symbol periods dedicated to training. In MIMO mode, the training symbols are divided between antennas, orthogally in time. In SISO mode, every training period is used for estimating the single channel. See the OFDM frame format documentation for more information.


Rx_PktDet_Delay

Dir: Read/Write

Fields:

PKT_DET_DELAY

(Bits 21:16 - UFix6_0) This integer sets the delay (in samples) between a long correlation threshold crossing and the start of coarse carrier frequency offset calculation.

SYMBOM_TIMING_OFFSET

(Bits 12:7 - UFix6_0) This integer sets the nominal symbol timing offset. This value is used as the starting index for the FFT calculation of each received OFDM symbol. This value must be less than the cyclic prefix length.

PKT_DET_DELAY

(Bits 6:0 - UFix7_0) This integer sets the delay inserted between the course packet detection signal and the start of receiver processing. This delay should correspond to the time difference between packet detection and the start of the preamble's fourth short training symbol.


Rx_PktDet_LongCorr_Params

Dir: Read/Write

Fields:

CORR_SET_TIMING

(Bits 31:16 - UFix16_0) This integer sets sample index used when a long correlation event occurs. The receiver uses a large counter to track packet timing. This counter increments with each sample, starting with course packet detection. When the long correlator crosses its threshold, the counter is set to this value.

CORR_THRESHOLD

(Bits 15:0 - UFix16_0) This integer sets the long correlation threshold used during fine packet detection and symbol timing.


Rx_PktDone_Reset

Dir: Read/Write

Fields:

PLBPKTBUF_RX_OFFSET

(Bits 11:10 - UFix2_0) This integer selects the sub-packet-buffer for received packets in the PLB BRAM. The Rx PHY will write incoming packet payloads to this sub-buffer.

PLBPKTBUF_TX_OFFSET

(Bits 9:8 - UFix2_0) This integer selects the sub-packet-buffer for transmitted packets in the PLB BRAM. The Tx PHY will read packet payload for transmission from this sub-buffer.

EN_BADPKT_INT

(Bit 5) Enables the bad packet interrupt output. The interrupt is raised via the top-level output rx_int_badpkt. Bad packets are defined as packets which fail the CRC checksum calculation.

EN_GOODPKT_INT

(Bit 4) Enables the good packet interrupt output. The interrupt is raised via the top-level output rx_int_goodpkt. Good packets are defined as packets which pass the CRC checksum calculation.

RST_BADPKT_INT

(Bit 1) Resets the bad packet interrupt. The application must assert & de-assert this bit after processing a bad packet.

RST_GOODPKT_INT

(Bit 0) Resets the good packet interrupt. The application must assert & de-assert this bit after processing a good packet.


Rx_pktByteNums

Dir: Read/Write

Fields:

PKT_BYTENUM_NUMBYTES_LSB

(Bits 15:8 - UFix8_0) Recevied header byte index for lower 8 bits of numPayloadBytes value

PKT_BYTENUM_NUMBYTES_MSB

(Bits 23:16 - UFix8_0) Recevied header byte index for upper 8 bits of numPayloadBytes value

PKT_BYTENUM_MODMASKS

(Bits 31:24 - UFix8_0) Recevied header byte index for dynamic modulation modMasks value


Rx_pktDet_Tresholds

Dir: Read/Write

Fields:

PKTDET_ENERGY_THRESH

(Bits 19:8 - UFix12_5) This fixed-point value is the energy threshold used for the internal packetion system.

PKTDET_CORR_THRESH

(Bits 7:0 - UFix8_7) This fixed-point value is the correlation threshold used for the internal packetion system.


TxRx_FFT_Scaling

Dir: Read/Write

Fields:

RX_FFT_SCALING_0

(Bits 11:10 - UFix2_0) This integer sets the scaling after the first stage of the FFT calculation.

RX_FFT_SCALING_1

(Bits 9:8 - UFix2_0) This integer sets the scaling after the middle stage of the FFT calculation.

RX_FFT_SCALING_2

(Bits 7:6 - UFix2_0) This integer sets the scaling after the last stage of the FFT calculation.

TX_FFT_SCALING_0

(Bits 5:4 - UFix2_0) This integer sets the scaling after the first stage of the IFFT calculation.

TX_FFT_SCALING_1

(Bits 3:2 - UFix2_0) This integer sets the scaling after the middle stage of the IFFT calculation.

TX_FFT_SCALING_2

(Bits 1:0 - UFix2_0) This integer sets the scaling after the last stage of the IFFT calculation.


Rx_FreqOffFilt_KI

Dir: Read/Write

Fields:

CFO_FILT_COEF_I

(Bits 31:0 - UFix32_32) Integral path coefficient for the loop filter in the carrier frequency offset pilot phase tracking system.


Rx_FreqOffFilt_KP

Dir: Read/Write

Fields:

CFO_FILT_COEF_P

(Bits 31:0 - UFix32_32) Proportional path coefficient for the loop filter in the carrier frequency offset pilot phase tracking system.


Rx_PhaseNoiseTrack_K

Dir: Read/Write

Fields:

Rx_PhaseNoiseTrack_K

(Bits 31:0 - UFix32_32) Scaling constant for phase noise tracking system; should be 0.0095215 (0x2700000) for normal operation.


Rx_PhaseNoiseTrack_Kalpha

Dir: Read/Write

Fields:

Rx_PhaseNoiseTrack_Kalpha

(Bits 31:0 - UFix32_32) Scaling constant for phase noise tracking system; should be 0.5 (0x40000000) for normal operation. This register will be removed in a future PHY revision.


Rx_PhaseNoiseTrack_Kbeta

Dir: Read/Write

Fields:

Rx_PhaseNoiseTrack_Kbeta

(Bits 31:0 - UFix32_32) Scaling constant for phase noise tracking system; should be 0.5 (0x40000000) for normal operation. This register will be removed in a future PHY revision.


Rx_PhaseNoiseTrack_Kgamma

Dir: Read/Write

Fields:

Rx_PhaseNoiseTrack_Kgamma

(Bits 31:0 - UFix32_32) Scaling constant for phase noise tracking system; should be 0.5 (0x40000000) for normal operation. This register will be removed in a future PHY revision.


Rx_Constellation_Scaling

Dir: Read/Write

Fields:

ANT_B_SCALING

(Bits 31:16 - UFix16_11) This fixed-point value is used to scale the output of the equalizer for antenna B before symbols are detected. This scaling is used to fit the received constellation to the pre-defined hard decision boundaries used during symbol detection.

ANT_A_SCALING

(Bits 15:0 - UFix16_11) This fixed-point value is used to scale the output of the equalizer for antenna A before symbols are detected. This scaling is used to fit the received constellation to the pre-defined hard decision boundaries used during symbol detection.


Tx_PreambleScaling

Dir: Read/Write

Fields:

PREAMBLE_SCALING

(Bits 15:0 - UFix16_16) This fraction sets the scaling of the preamble. The preamble is stored with a full-scale swing on [-1, +1]. The actual transmitted preamble is scaled by this fration.


Tx_Pilots_Index1

Dir: Read/Write

Fields:

PILOT1_INDEX_1

(Bits 5:0 - UFix6_0) Subcarrier index for first copy of pilot tone 1. This index should be symmetric about DC with PILOT1_INDEX_2 below.

PILOT1_INDEX_2

(Bits 21:16 - UFix6_0) Subcarrier index for second copy of pilot tone 1. This index should be symmetric about DC with PILOT1_INDEX_1 above.


Tx_Pilots_Index2

Dir: Read/Write

Fields:

PILOT2_INDEX_1

(Bits 5:0 - UFix6_0) Subcarrier index for first copy of pilot tone 2. This index should be symmetric about DC with PILOT2_INDEX_2 below.

PILOT2_INDEX_2

(Bits 21:16 - UFix6_0) Subcarrier index for second copy of pilot tone 2. This index should be symmetric about DC with PILOT2_INDEX_1 above.


Tx_Pilots_Value1

Dir: Read/Write

Fields:

PILOT1_ANTA_VALUE

(Bits 15:0 - Fix16_15) Value for pilot tone 1 on antenna A.

PILOT1_ANTB_VALUE

(Bits 31:16 - Fix16_15) Value for pilot tone 1 on antenna B.


Tx_Pilots_Value2

Dir: Read/Write

Fields:

PILOT2_ANTA_VALUE

(Bits 15:0 - Fix16_15) Value for pilot tone 2 on antenna A.

PILOT2_ANTB_VALUE

(Bits 31:16 - Fix16_15) Value for pilot tone 2 on antenna B.


Tx_OFDM_SymCounts

Dir: Read/Write

Fields:

NUM_TRAINING_SYMS

(Bits 7:0 - UFix8_0) Number of training symbols transmitted before the payload in each packet. This value can be changed per packet, but must remain constant during a transmission.

NUM_BASERATE_SYMS

(Bits 15:8 - UFix8_0) Number of base rate symbols sent per packet. A base rate symbol is modulated at a different rate than the full rate symbols which follow. Also, identical base rate symbols are sent from both antennas; true multiplexing only applies to full rate symbols.

NUM_PYLD_SYMS

(Bits 31:16 - UFix16_0) Number of full rate OFDM symbols in the transmitted packet. Full rate symbols are modulated at a faster rate and are sent multiplexed across both antennas. This number must be even when MIMO mode is enabled. The transmitter will pad the payload to fill unoccupied space in full OFDM symbols.


Tx_Start_Reset_Control

Dir: Read/Write

Fields:

TX_RESET

(Bit 0 - UFix1_0) Global active-high reset for the transmitter subsystem. When asserted, all internal state in the transmitter will be cleared, except the register bank.

TX_START

(Bit 1 - UFix1_0) Trigger for beginning a packet transmission. This register bit acts exactly like the tx_starttransmit input port. Only one trigger option (port or register) should be used per packet.

TX_PKTDONE_RESET

(Bit 2 - UFix1_0) Clears the state of the Tx_PktDone register. User code should toggle this register high/low after each packet transmission.


Tx_ControlBits

Dir: Read/Write

Fields:

SISO_MODE

(Bit 0) Enables SISO mode in the transmitter. This option can be enabled per packet and will only function correctly when used with a receiver in SISO mode.

DISABLE_ANTB_PREAMBLE

(Bit 2) When asserted, disables the transmission of a preamble from antenna B.

EN_PILOT_SCRAMBLING

(Bit 3) Enables 802.11-style pilot tone scrambling. When used, pseudo-random sign changes will be applied per OFDM symbol.

ANTB_PREAMBLE_SHIFT

(Bits 7:4 - UFix4_0) Integer number of samples to shift antenna B's preamble; the shift is circular over the full preamble.

TX_SISO_ANTB

(Bit 8) Uses antenna B when in SISO mode; ignored when in MIMO mode.


Rx_Gains

Dir: Read/Write

Fields:

RX_GAINS_ANTA_BB

(Bits 4:0 - UFix5_0) Antenna A baseband gain, as set by AGC after packet detection.

RX_GAINS_ANTA_RF

(Bits 6:5 - UFix1_0) Antenna A RF gain, as set by AGC after packet detection.

RX_GAINS_ANTB_BB

(Bits 12:8 - UFix5_0) Antenna B baseband gain, as set by AGC after packet detection.

RX_GAINS_ANTB_RF

(Bits 14:13 - UFix1_0) Antenna B RF gain, as set by AGC after packet detection.


Rx_BER_Errors

Dir: Read-only

Fields:

BER_ERRORS

(Bits 31:0 - UFix32_0) Total number of bit errors detected. BER measurements are only useful when the default packet is repeatedly transmitted.


Rx_BER_TotalBits

Dir: Read-only

Fields:

BER_TOTALBITS

(Bits 31:0 - UFix32_0) Total number of bits received. Divide BER_ERRORS by this field to calculate the bit error rate.


Rx_packet_done

Dir: Read-only

Fields:

RX_GOODPKT

(Bit 0 - UFix1_0) Active high when a good packet is received. This field will only go high when EN_GOODPKT_INT is enabled and must be cleared by asserting RST_GOODPKT_INT.

RX_BADPKT

(Bit 1 - UFix1_0) Active high when a bad packet is received. This field will only go high when EN_BADPKT_INT is enabled and must be cleared by asserting RST_BADPKT_INT.


Tx_PktDone

Dir: Read-only

TX_PKT_DONE

(Bit 0 - UFix1_0) Active high when a packet transmission is complete. This field can be cleared by toggling TX_PKTDONE_RESET.

Last modified 12 years ago Last modified on Sep 27, 2007, 11:43:05 AM