---- == Register bits ![31:16] == {{{ #!html
Reg Dir Addr 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Rx_ControlBits Read/Write 0x0 RESERVED
Rx_GlobalReset Read/Write 0x4 RESERVED
Rx_OFDM_SymbolCounts Read/Write 0x8 NUM_BASERATE_SYMS
Rx_PktDet_Delay Read/Write 0xC RESERVED
Rx_PktDet_LongCorr_Params Read/Write 0x10 CORR_SET_TIMING
Rx_PktDone_Reset Read/Write 0x14 RESERVED
Rx_symbolTimingOffset Read/Write 0x18 RESERVED
Rx_FreqOffFilt_KI Read/Write 0x1C CFO_FILT_COEF_I (MSB)
Rx_FreqOffFilt_KP Read/Write 0x20 CFO_FILT_COEF_P (MSB)
Rx_Constellation_Scaling Read/Write 0x24 ANT_B_SCALING
Rx_FFT_Scaling Read/Write 0x28 RESERVED
Rx_pktDet_Corr_Thresh Read/Write 0x2C RESERVED
Rx_pktDet_Energy_Thresh Read/Write 0x30 RESERVED
Tx_FFT_Scaling Read/Write 0x34 RESERVED
Tx_PreambleScaling Read/Write 0x38 RESERVED
Tx_NumPayloadBytes Read/Write 0x3C RESERVED
Tx_RandomPayload_ModSel Read/Write 0x40 RESERVED
Tx_Pilots_Index1 Read/Write 0x44 RESERVED PILOT1_INDEX_2
Tx_Pilots_Index2 Read/Write 0x48 RESERVED PILOT2_INDEX_2
Tx_Pilots_Value1 Read/Write 0x4C PILOT1_ANTB_VALUE
Tx_Pilots_Value2 Read/Write 0x50 PILOT2_ANTB_VALUE
Tx_OFDM_SymCounts Read/Write 0x54 NUM_PYLD_SYMS
Tx_Start_Reset_Control Read/Write 0x58 RESERVED
Tx_ControlBits Read/Write 0x5C RESERVED
Rx_BER_Errors RO 0x60 BER_ERRORS (MSB)
Rx_BER_TotalBits RO 0x64 BER_TOTALBITS (MSB)
Rx_packet_done RO 0x68 RESERVED
Tx_PktDone RO 0x6C RESERVED
}}} ---- == Register bits ![15:0] == {{{ #!html
Reg Dir Addr 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Rx_ControlBits Read/Write 0x0 RESERVED CFO_USE_LONGCORR CFO_USE_STS CFO_USE_LTS CFO_BYPASS INT_PKTDET_EN EXT_PKTDET_EN REQ_SHORT_CORR REQ_TWO_LONG_CORR SISO_MODE RESERVED DYN_PKT_LENGTHS REQ_LONG_CORR BER_RESET
Rx_GlobalReset Read/Write 0x4 RESERVED RX_RESET
Rx_OFDM_SymbolCounts Read/Write 0x8 NUM_TRAINING_SYMS
Rx_PktDet_Delay Read/Write 0xC RESERVED PKT_DET_DELAY
Rx_PktDet_LongCorr_Params Read/Write 0x10 CORR_TRESHOLD
Rx_PktDone_Reset Read/Write 0x14 RESERVED EN_BADPKT_INT EN_GOODPKT_INT RESERVED RST_BADPKT_INT RST_GOODPKT_INT
Rx_symbolTimingOffset Read/Write 0x18 RESERVED SYMBOM_TIMING_OFFSET
Rx_FreqOffFilt_KI Read/Write 0x1C CFO_FILT_COEF_I (LSB)
Rx_FreqOffFilt_KP Read/Write 0x20 CFO_FILT_COEF_P (LSB)
Rx_Constellation_Scaling Read/Write 0x24 ANT_A_SCALING
Rx_FFT_Scaling Read/Write 0x28 RESERVED RX_FFT_SCALING_0 RX_FFT_SCALING_1 RX_FFT_SCALING_2
Rx_pktDet_Corr_Thresh Read/Write 0x2C RESERVED PKTDET_CORR_THRESH
Rx_pktDet_Energy_Thresh Read/Write 0x30 RESERVED PKTDET_ENERGY_THRESH
Tx_FFT_Scaling Read/Write 0x34 RESERVED TX_FFT_SCALING_0 TX_FFT_SCALING_1 TX_FFT_SCALING_2
Tx_PreambleScaling Read/Write 0x38 PREAMBLE_SCALING
Tx_NumPayloadBytes Read/Write 0x3C RESERVED NUM_BYTES
Tx_RandomPayload_ModSel Read/Write 0x40 RESERVED RAND_PLD_MOD_SEL
Tx_Pilots_Index1 Read/Write 0x44 RESERVED PILOT1_INDEX_1
Tx_Pilots_Index2 Read/Write 0x48 RESERVED PILOT2_INDEX_1
Tx_Pilots_Value1 Read/Write 0x4C PILOT1_ANTA_VALUE
Tx_Pilots_Value2 Read/Write 0x50 PILOT2_ANTA_VALUE
Tx_OFDM_SymCounts Read/Write 0x54 NUM_BASERATE_SYMS NUM_TRAINING_SYMS
Tx_Start_Reset_Control Read/Write 0x58 RESERVED TX_PKTDONE_RESET TX_START TX_RESET
Tx_ControlBits Read/Write 0x5C RESERVED EN_PILOT_SCRAMBLING DISABLE_ANTB_PREAMBLE RANDOM_PYLD SISO_MODE
Rx_BER_Errors RO 0x60 BER_ERRORS (LSB)
Rx_BER_TotalBits RO 0x64 BER_TOTALBITS (LSB)
Rx_packet_done RO 0x68 RESERVED RX_BADPKT_DONE RX_GOODPKT_DONE
Tx_PktDone RO 0x6C RESERVED TX_PKT_DONE
}}} Dir: Read/Write ---- == Rx_ControlBits == === Address: 0x0 === === Dir: Read/Write === === Fields: === {{{ #!html }}} '''CFO_USE_LONGCORR''' ''(bit 12)'':: Enables the use of the long correlator to control the timing of the carrier frequency offset estimation based on the long training symbols. This must be set to 1 for normal operation. '''CFO_USE_STS''' ''(bit 11)'':: Enables carrier frequency offset estimation based on the preamble's short training symbols. When using high-quality oscillators, this can be disabled to improve CFO estimation performance. '''CFO_USE_LTS''' ''(bit 10)'':: Enables carrier frequency offset estimation based on the preamble's long training symbols. Must be set to 1 for normal operation. '''CFO_BYPASS''' ''(bit 9)'':: When set to 1, CFO correction is bypassed. This should only be used when driving two nodes from a common reference clock during PHY debugging. '''INT_PKTDET_EN''' ''(bit 8)'':: Enables the internal packet detection block. This should only be used when debugging the PHY over a wire when the external packet detector is not being used. '''EXT_PKTDET_EN''' ''(bit 7)'':: Enables external packet detection via the [wiki:OFDM/MIMO/Docs/ModelPorts ''rx_extpktdet'' port] '''REQ_SHORT_CORR''' ''(bit 6)'':: Requires either internal or external packet detection in order to begin processing a packet. When disabled, the receiver will begin processing packets when trigged only by the long correlator. '''REQ_TWO_LONG_CORR''' ''(bit 5)'':: Requires two threshold crossings from the long correlator, spaced exactly 64 cycles apart. When enaled, this makes packet detection more robust at the cost of more false negative detections. '''SISO_MODE''' ''(bit 4)'':: Enables single-antenna (SISO) mode in the receiver. In this mode, only packets transmitted in SISO mode will be properly received. '''DYN_PKT_LENGTHS''' ''(bit 2)'':: Enables dynamic packet lengths. This should be 1 for normal operation. When disabled, the receiver assumes every packet is a fixed length. This is useful during PHY debugging and BER testing. '''REQ_LONG_CORR''' ''(bit 1)'':: Requires a threshold crossing in the long correlator for packet detection. This must be one for reliable operation. '''BER_RESET''' ''(bit 0)'':: When enabled, the BER calculation engine is held in reset. This should be 0 only during BER testing. ---- == Rx_GlobalReset == ==== Address: 0x4 ==== ==== Dir: Read/Write ==== ---- == Rx_OFDM_SymbolCounts == ==== Address: 0x8 ==== ==== Dir: Read/Write ==== ---- == Rx_PktDet_Delay == ==== Address: 0xC ==== ==== Dir: Read/Write ==== ---- == Rx_PktDet_LongCorr_Params == ==== Address: 0x10 ==== ==== Dir: Read/Write ==== ---- == Rx_PktDone_Reset == ==== Address: 0x14 ==== ==== Dir: Read/Write ==== ---- == Rx_symbolTimingOffset == ==== Address: 0x18 ==== ==== Dir: Read/Write ==== ---- == Rx_FreqOffFilt_KI == ==== Address: 0x1C ==== ==== Dir: Read/Write ==== ---- == Rx_FreqOffFilt_KP == ==== Address: 0x20 ==== ==== Dir: Read/Write ==== ---- == Rx_Constellation_Scaling == ==== Address: 0x24 ==== ==== Dir: Read/Write ==== ---- == Rx_FFT_Scaling == ==== Address: 0x28 ==== ==== Dir: Read/Write ==== ---- == Rx_pktDet_Corr_Thresh == ==== Address: 0x2C ==== ==== Dir: Read/Write ==== ---- == Rx_pktDet_Energy_Thresh == ==== Address: 0x30 ==== ==== Dir: Read/Write ==== ---- == Tx_FFT_Scaling == ==== Address: 0x34 ==== ==== Dir: Read/Write ==== ---- == Tx_PreambleScaling == ==== Address: 0x38 ==== ==== Dir: Read/Write ==== ---- == Tx_NumPayloadBytes == ==== Address: 0x3C ==== ==== Dir: Read/Write ==== ---- == Tx_RandomPayload_ModSel == ==== Address: 0x40 ==== ==== Dir: Read/Write ==== ---- == Tx_Pilots_Index1 == ==== Address: 0x44 ==== ==== Dir: Read/Write ==== ---- == Tx_Pilots_Index2 == ==== Address: 0x48 ==== ==== Dir: Read/Write ==== ---- == Tx_Pilots_Value1 == ==== Address: 0x4C ==== ==== Dir: Read/Write ==== ---- == Tx_Pilots_Value2 == ==== Address: 0x50 ==== ==== Dir: Read/Write ==== ---- == Tx_OFDM_SymCounts == ==== Address: 0x54 ==== ==== Dir: Read/Write ==== ---- == Tx_Start_Reset_Control == ==== Address: 0x58 ==== ==== Dir: Read/Write ==== ---- == Tx_ControlBits == ==== Address: 0x5C ==== ==== Dir: Read/Write ==== ---- == Rx_BER_Errors == ==== Address: 0x60 ==== ==== Dir: Read-only ==== ---- == Rx_BER_TotalBits == ==== Address: 0x64 ==== ==== Dir: Read-only ==== ---- == Rx_packet_done == ==== Address: 0x68 ==== ==== Dir: Read-only ==== ---- == Tx_PktDone == ==== Address: 0x6C ==== ==== Dir: Read-only ====