MIMO OFDM | Documentation? | OFDM Core Hardware System Requirements

The WARP MIMO OFDM core is just one part of a complete wireless networking design. A number of additional peripheral cores must be integrated to construct a full wireless design. An example of a full system assembly is shown in the figure below.

Some of the additional blocks in this diagram are described below. See the OFDM Reference Design for a full EDK project which integrates all of these cores into a fully-functional design.

Automatic Gain Control (AGC)

This core implements the front-end gain control algorithm which is responsible for setting the gain levels inside the radio transceiver. The AGC algorithm begins processing when the packet detector signals the beginning of a packet. Once it settles to the optimum gain values, it holds these values until reset by the OFDM core.

Radio Controller

This is a custom peripheral which controls the radio transceiver and D/A converter on the WARP radio daughtercard. This core is driven from user code via the radio controller driver's API.

Radio Bridge

This is a simple core which interfaces the radio controller, AGC, packet detector and OFDM cores to the physical FPGA pins which connect to each WARP daughtercard slot. This core contains very little logic and is used primarily to facilitate automatic constraint generation via the WARP FPGA board's XBD file.

Last modified 13 years ago Last modified on Aug 29, 2009, 9:47:35 PM