Changes between Version 2 and Version 3 of OFDM/MIMO/Docs/SystemRequirements


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Timestamp:
Aug 29, 2009, 9:47:35 PM (15 years ago)
Author:
murphpo
Comment:

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  • OFDM/MIMO/Docs/SystemRequirements

    v2 v3  
    55[[Image(OFDM/MIMO/Docs/Images:OFDM_System.png, 550)]]
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    7 Each of the additional blocks in this diagram are described below. See the [wiki:OFDM/MIMO#Examples MIMO OFDM Examples] for full EDK projects which implement this system.
    8 
    9 ''Packet Detector''
    10   A peripheral dedicated to detecting the beginning of a received packet. The WARP MIMO packet detector uses the received signal strength indicator (RSSI) from the radio daughtercard to detect incoming packets. This block is connected to both the AGC and OFDM cores, which use the packet detection signal to begin processing a new packet.
     7Some of the additional blocks in this diagram are described below. See the [wiki:OFDMReferenceDesign OFDM Reference Design] for a full EDK project which integrates all of these cores into a fully-functional design.
    118
    129''Automatic Gain Control (AGC)''
     
    1815''Radio Bridge''
    1916  This is a simple core which interfaces the radio controller, AGC, packet detector and OFDM cores to the physical FPGA pins which connect to each WARP daughtercard slot. This core contains very little logic and is used primarily to facilitate automatic constraint generation via the WARP FPGA board's XBD file.
    20 
    21 ''Interrupt Controler'', ''Timers'', ''Ethernet'' & ''External SRAM''
    22   These are standard peripheral cores provided by Xilinx in the Embedded Development Kit.