| 3 | |
| 4 | == OFDM Models Overview == |
| 5 | Our SISO OFDM transceiver is implemented as two Simulink models built using Xilinx's System Generator for DSP. Both models are designed from scratch for real-time, wideband operation on the WARP hardware. The models have top-level interfaces to the WARP radio board's Tx/Rx analog converters. They also utilize an OPB interface for data exchange and control by the embedded PowerPC in the WARP FPGA. |
| 6 | |
| 7 | == Performance == |
| 8 | Some basic performance paramters are listed below. This page will be updated as we further verify and extend the models in hardware. |
| 9 | |
| 10 | '''Bandwidth:''' |
| 11 | The effective bandwidth is currently 10 MHz. The ADC/DAC sampling rate is actually 50 MHz; interpolation/decimation filters are included in the models to achieve this rate change. |
| 12 | |
| 13 | '''Moduation:''' |
| 14 | Both models support flexible modulation schemes, allowing individual subcarriers to carry [0, 1, 2, 4, 6, 8] bits. In other words, any combination of 0, BPSK, QPSK, 16/64/256 QAM can be used per packet. We have fully tested a QPSK-only system in hardware, loading 48 of 64 subcarriers with user data. |
| 15 | |
| 16 | '''Data rate:''' |
| 17 | We have tested a 12 Mbps PHY configuration over-the-air (10 MHz bandwidth with 48 data-bearing subcarriers using QPSK modulation). We have also tested a 16 QAM system in hardware (running at 24 Mbps) and are in the process of fully verifying its operation now. |