wiki:OFDMReferenceDesign/Changelog

WARP OFDM Reference Design Revision History

OFDM Reference Design v18.1 (2012-Nov-16)

This is a minor update for WARP v3 only, to correct a few small things in the v18.0 design.

  • Updated constraints for ETH_A MDIO pins
  • Swapped order of user DIP switch signals, so LSB is now right-most switch
  • Updated to the latest versions of the WARP v3 support cores (radio_controller, w3_userio, etc.)

There is no change in C code or in PHY functionality from v18.0. This design will inter-operate with OFDM Reference Design v16.2 on WARP v1 and v18.0 on WARP v2.

Downloads:

Hardware Release Date Posted ISE Ver Arch Download
WARP v3 18.1 16-Nov-2012 13.4 MB/PLB w3_OFDM_ReferenceDesign_v18p1.zip (17MB)

OFDM Reference Design v18.0 (2012-Aug-29)

This is our first OFDM Reference Design with support for WARP v3 hardware. The underlying MAC and PHY designs are identical in the WARP v2 and v3 designs. The v18.0 projects will inter-operate at RF between hardware generations.

The WARP v3 hardware project is based on the WARP v3 On Board Peripherals template project, modified with the custom PHY cores and an extra PLB running at 40MHz.

We've slightly revised the folder structure for bundling the XPS and SDK projects. Please see SDK notes for instructions on re-creating a working SDK workspace for this design.

Both projects below are built in Xilinx ISE 13.4. It may be possible to open them in newer versions of ISE, but we have not tried this.

Hardware Changes

  • Updated auto-correlation packet detector logic for better dynamic range through the pipeline
  • Added WARP v3 support
    • Ported OFDM PHY, AGC and rate change filters to Virtex-6 FPGA
    • Ported to new support peripherals (radio_controller, w3_ad_controller, etc.) for WARP v3

Software Changes

  • warpmac/warpphy are separate code bases for WARP v2 and v3 in this design. This is a temporary situation. We are planning to rework the WARPMAC framework so a common code base works across hardware versions.
  • Updated default thresholds in MACs, to account for new RSSI ADC on WARP v3

Downloads:

Support: Porting the OFDM reference design to WARP v3 was a big project, and it's entirely possible we overlooked something. We welcome any feedback (preferably via the forums).


OFDM Reference Design v17.0 (2012-May-03)

This is our first attempt at an OFDM Reference Design built in the Xilinx 13.4 tools. There are no MAC/PHY changes from v16.1. In fact we tested the v17.0 project on a WARP v2 kit communicating over-the-air with a WARP v1 kit running OFDM Reference Design v16.1.

We're still learning the 13.4 tools- they have changed a lot since 10.1. As such the project below should be considered experimental, likely to change in code & structure as we continue learning the tools.

We think the folder structure we've used is a good way to distribute the XPS and SDK projects (it mimics Xilinx's approach for reference designs targeting their dev boards). Unfortunately there is no good way to distribute a ready-to-go SDK workspace. The .zip file below includes all the software projects and launch configurations, but you will need to re-create a local SDK workspace. Please see SDK notes for preliminary instructions.

Downloads:


OFDM Reference Design v16.2 (2012-Aug-31)

This is a release for WARP v1 (Virtex-II Pro FPGA) hardware only. The only change from v16.1 is back-porting the updated auto-correlation packet detector logic used in the v18.0 design for WARP v2/v3. This design inter-operates at RF with OFDM Reference design v16.1 (on other WARP v1 kits) and v18.0 (on WARP v2 and v3 kits).

Downloads:


OFDM Reference Design v16.1 (2011-Apr-26)

The code and models for this design correspond to svn rev 1663.

Download the full XPS projects:

Both projects were built using the latest versions of the 10.1 release of the Xilinx tools (ISE 10.1.03 + IP3, EDK 10.1.03, Sysgen 10.1.3.1386).

Hardware Changes

  • Added new packet detection subsystem, based on the standard Schmidl/Cox preamble auto-correlation algorithm. This subsystem operates in parallel to the existing RSSI-based detector. The auto-correlation detector cannot detect high-SNR receptions, due to corruption of I/Q pre-AGC, but works well for low-SNR receptions.
  • Fixed random payload capture bug (used for WARPnet BER testing)

Software Changes

  • Updated warpphy/warpmac to reflect changes to registers in the PHY

Using the Design

  • Same as v16.0 below

OFDM Reference Design v16.0 (2011-Feb-17)

The code and models for this design correspond to svn rev 1626.

Download the full XPS projects:

Both projects were built using the latest versions of the 10.1 release of the Xilinx tools (ISE 10.1.03 + IP3, EDK 10.1.03, Sysgen 10.1.3.1386).

Notes (please read!)
The OFDM Reference Design now includes channel coding. The PHY implements a K=7 convolutional code with support for four code rates (1/2, 2/3, 3/4 and 1). This is the same code used by 802.11a/g. When coding is enabled, packet headers are sent as 1/2 rate coded QPSK, and payloads are encoded according to the codeRate field in the header. The payload code rate is configured per-packet; the receiver configures its decoder based on the codeRate field in the header. Payloads can be modulated with BPSK, QPSK or 16-QAM (all 12 combinations of payload modulation/code rate are supported).

The PHY is identical for FPGA v1 and v2. The same .mdl file (ofdm_txrx_supermimo_coded.mdl) is used to generate the pcores for both versions. The only difference is the target device selected in the System Generator token (XC2VP70-FF1517-6 for v1 and XC4VFX100-FF1517-11 for v2).

Because of limitations in the number of multipliers in the Virtex-4 FPGA, the decimation filters in the rate_change_filters pcore use non-embedded multipliers (i.e. implemented in fabric) in the v2 design. The rate_change_filter source model is in the repository (/ResearchApps/PHY/MIMO_OFDM/Rate Change Filters), along with a .m script which enables/disables embedded multipliers in the decimation filters.

We have tested the coded PHY with every combination of code and modulation rate and many packet lengths. We found some bugs in earlier iterations and believe they are all fixed. We have not used this design for extensive over-the-air experiments yet (these are ongoing, part of our current research work). We don't expect any problems, and are eager to hear any feedback from other groups using the design in their work.

Hardware Changes

  • Integrated convolutional channel coding, with configurable coding rate per packet
  • Added decimation filters to PHY I/Q input
  • Relocated rate change filters to separate pcore (sits between radio_bridges and AGC/PHY)

Software Changes

  • Added codeRate field in packet transmission functions
  • Updated warpphy/warpmac to reflect changes to registers in the PHY

Using the Design

  • The included download-csmamac.bit file implements CSMAMAC; download-nomac.bit implements NOMAC. Both are ready to download to WARP SISO or MIMO Kits.
  • The included download-csmamac.ace or download-nomac.ace can be copied directly to a CompactFlash card (without using iMPACT) to program kits via the SystemACE CF interface.
  • The CSMAMAC code uses the UART to control various parameters at run time. Use a terminal emulator set to 57600bps. The following commands are implemented by default:
    • P/p : Increase/decrease the packet detection energy threshold by 100
    • D/d : Increase/decrease the packet detection required minimum energy duration by 1
    • C/c : Increase/decrease the carrier sensing energy threshold by 100
    • F/f : Increase/decrease the 2.4GHz center frequency by 1 channel
    • S/s : Use SISO via the radio in slot 3/2
    • A : Use Alamouti 2x2 (2 transmit antennas, selection diversity between 2 receive antennas)
    • 1/2/4 : Use BPSK/QPSK/16-QAM for the full-rate modulation scheme for all transmitted payloads
    • 7/8/9/0 : Use [1/2, 2/3, 3/4, 1] coding rate for all transmitted payloads (rate 1 = no coding)
    • You can add other commands to tweak your own parameters in uartRecv_callback function
  • The four user LEDs are programmed by default to toggle based on packet receptions. The top two LEDs will toggle for each good packet received. The bottom two LEDs will toggle for each bad header or bad payload received.
  • The right seven-segment display is programmed to show the node's ID on boot (set by the DIP switch); the left displays shows the sequence number of received packets.

Previous Releases

Last modified 4 years ago Last modified on Jan 3, 2014, 9:23:23 AM