wiki:OFDMReferenceDesign/Changelog

Version 18 (modified by murphpo, 16 years ago) (diff)

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OFDM Reference Design History

OFDM Reference Design v11 (coming soon...)

Hardware Changes

  • Updated clock config core to latest version (fixes bad default values for en/disabled outputs)
  • Replaced ofdm_timer with new warp_timer peripheral (now includes four independent timers)
  • Reworked PHY to clock Rx FFT at system clock (40MHz).
    • This reduces the Rx latency by ~4µsec; DATA-ACK turnaround now 19.8µsec.
    • This also helps CFO, allowing the pilot tones to apply phase corrections one OFDM symbol earlier.
  • Redesigned pilot tone phase averaging to reduce intra-symbol variance.
  • Re-added shared memories for flexible Tx/Rx modulation (these were removed in v10 due to Sysgen 10.1.00 limitations).
  • Added User I/O board controller
  • Added interrupt for UART
  • Connected reset for secondary PLB46 (fixing bug found by patel_gaurav90)

Software Changes

  • New RTS/CTS implementation by Keith Wilhelm (undergrad intern in the CMC Lab)
  • Updated WARPMAC/WARPPHY with support for PHY changes
    • Updated timer wrapper functions for new warp_timer hardware
    • Updated modulation control function for new buffer structure
    • New UART ISR and user callback registration functions
  • New debug "MAC" top-level code to control/observe/debug PHY in hardware
  • Added basic Rx statistics display via the User I/O board LCD screen
  • Moved interactive debug menu to UART interrupt callback (instead of in main while(1) loop)
  • Updated AGC thresholds to better values (based on empirical tests)
  • Fixed support for MIMO mode in WARPMAC/WARPPHY (now correctly calculates PHY parameters in either SISO or MIMO mode)

OFDM Reference Design v10 (2008-Jul-17)

  • Known issue: see this forum post for details; this will be fixed in ref design v11
  • Download the XPS project: OFDM_ReferenceDesign_v10.zip
  • Built using cores and code as of repository revision 1010
  • This design requires version 10.1.02 of the Xilinx tools
  • Data-ACK turnaround time is now 23µs (as measured by the fall of data Tx to rise of ACK Tx)

Hardware Changes

  • Xilinx deprecated the OPB and PLB34 busses. PLB46 is the new (and only) bus standard used in this design
  • The System Generator cores (OFDM transceiver, timer, packet detector & AGC) were created using Sysgen's new PLB46 export flow; sysgen2opb is no longer required
  • Xilinx did not port the plb_ethernet EMAC forward to PLB46. This design uses the xps_ethernetlite EMAC instead, customized to enable promiscuous mode (i.e. no receive address filtering)
  • The xps_centraldma pcore is used to handle DMA (since the EMAC no longer provides its own DMA)
  • The OFDM transceiver has a new interrupt output indicating the reception of a bad header
  • Fixed a few logic bugs in the transceiver's handling of multiple interrupts
  • Merged all user I/O into single GPIO core (LEDs, hex displays, push buttons & DIP switch); a header file helps with the required bit masking/shifting. The XBD files have been updated to use the same user I/O scheme.

Software Changes

  • Ethernet is now operated exclusively in a polling mode for increased performance
  • WARPMAC/WARPPHY re-architected and cleaned; the code flows for transmitting and receiving packets are now consistent across various packet types
  • A layer of register access macros was added between WARPPHY and the OFDM cores; these macros adapt the old sysgen2opb register access code to the new Sysgen PLB46 export code. These macros will retired in a future revision.

OFDM Reference Design v09 (2008-Jun-11)

  • Download the XPS project: OFDM_ReferenceDesign_v09.zip
  • Built using cores and code as of repository revision 906
  • This version assumes a different location for TxDCO calibration information in the EEPROM of the radios. Please re-calibrate before running (instructions are here)
  • This will be the last reference design that will use the version 9 Xilinx tools. Reference Design v10 will use the version 10 Xilinx tools.
  • Updated warpmac/warpphy & csmamac
    • Header interrupts are used to pipeline receive processions (i.e. an ACK is constructed and loaded into a PHY before the packet is even completely received)
    • Fall of Tx data to rise of Tx ACK turn-around time reduced from 80 microseconds to 30 microseconds
    • By default, left and right push buttons use left and right radios respectively (only for MIMO WARP kits)
    • Numerous tweaks to MAC timing parameters

OFDM Reference Design v08 (2008-Feb-08)

  • Download the XPS project: OFDM_ReferenceDesign_v08.zip
  • Built using cores and code as of repository revision 834
  • Updated OFDM PHY
    • Added support for header-only packets (like ACKs); numFullRateSymbols can be zero
    • Last two bytes of header are now a 16-bit CRC of just the header
    • Added new interrupt output for good header; asserts for non-header-only packets when header CRC passes
    • Added TxDone interrupt output; asserts when a packet transmission finishes
    • Fixed bugs in dynamic modulation mask usage
  • Updated warpmac/warpphy & csmamac
    • Changes to support new PHY features
    • Added TxDone & GoodHeader interrupt handlers; unused in this version
    • Added lots of comments to the source code to better explain various MAC/PHY interactions