wiki:OFDMReferenceDesign/Changelog

Version 77 (modified by murphpo, 13 years ago) (diff)

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WARP OFDM Reference Design Revision History

OFDM Reference Design v16.0 (2011-Feb-17)

The code and models for this design correspond to svn rev 1626.

Download the full XPS projects:

Both projects were built using the latest versions of the 10.1 release of the Xilinx tools (ISE 10.1.03 + IP3, EDK 10.1.03, Sysgen 10.1.3.1386).

Notes (please read!)
The OFDM Reference Design now includes channel coding. The PHY implements a K=7 convolutional code with support for four code rates (1/2, 2/3, 3/4 and 1). This is the same code used by 802.11a/g. When coding is enabled, packet headers are sent as 1/2 rate coded QPSK, and payloads are encoded according to the codeRate field in the header. The payload code rate is configured per-packet; the receiver configures its decoder based on the codeRate field in the header. Payloads can be modulated with BPSK, QPSK or 16-QAM (all 12 combinations of payload modulation/code rate are supported).

The PHY is identical for FPGA v1 and v2. The same .mdl file (ofdm_txrx_supermimo_coded.mdl) is used to generate the pcores for both versions. The only difference is the target device selected in the System Generator token (XC2VP70-FF1517-6 for v1 and XC4VFX100-FF1517-11 for v2).

Because of limitations in the number of multipliers in the Virtex-4 FPGA, the decimation filters in the rate_change_filters pcore use non-embedded multipliers (i.e. implemented in fabric) in the v2 design. The rate_change_filter source model is in the repository (/ResearchApps/PHY/MIMO_OFDM/Rate Change Filters), along with a .m script which enables/disables embedded multipliers in the decimation filters.

We have tested the coded PHY with every combination of code and modulation rate and many packet lengths. We found some bugs in earlier iterations and believe they are all fixed. We have not used this design for extensive over-the-air experiments yet (these are ongoing, part of our current research work). We don't expect any problems, and are eager to hear any feedback from other groups using the design in their work.

Hardware Changes

  • Integrated convolutional channel coding, with configurable coding rate per packet
  • Added decimation filters to PHY I/Q input
  • Relocated rate change filters to separate pcore (sits between radio_bridges and AGC/PHY)

Software Changes

  • Added codeRate field in packet transmission functions
  • Updated warpphy/warpmac to reflect changes to registers in the PHY

Using the Design

  • The included download-csmamac.bit file implements CSMAMAC; download-nomac.bit implements NOMAC. Both are ready to download to WARP SISO or MIMO Kits.
  • The included download-csmamac.ace or download-nomac.ace can be copied directly to a CompactFlash card (without using iMPACT) to program kits via the SystemACE CF interface.
  • The CSMAMAC code uses the UART to control various parameters at run time. Use a terminal emulator set to 57600bps. The following commands are implemented by default:
    • P/p : Increase/decrease the packet detection energy threshold by 100
    • D/d : Increase/decrease the packet detection required minimum energy duration by 1
    • C/c : Increase/decrease the carrier sensing energy threshold by 100
    • F/f : Increase/decrease the 2.4GHz center frequency by 1 channel
    • S/s : Use SISO via the radio in slot 3/2
    • A : Use Alamouti 2x2 (2 transmit antennas, selection diversity between 2 receive antennas)
    • 1/2/4 : Use BPSK/QPSK/16-QAM for the full-rate modulation scheme for all transmitted payloads
    • 7/8/9/0 : Use [1/2, 2/3, 3/4, 1] coding rate for all transmitted payloads (rate 1 = no coding)
    • You can add other commands to tweak your own parameters in uartRecv_callback function
  • The four user LEDs are programmed by default to toggle based on packet receptions. The top two LEDs will toggle for each good packet received. The bottom two LEDs will toggle for each bad header or bad payload received.
  • The right seven-segment display is programmed to show the node's ID on boot (set by the DIP switch); the left displays shows the sequence number of received packets.

OFDM Reference Design v15.0 (2010-Aug-11)

The code and models for this design correspond to svn rev 1580 for the FPGA v1 design and svn rev 1585 for the FPGA v2 design.

Note: The PHY is functionally identical for FPGA v1 and v2. The v2 design uses HDL for 10 multipliers (in the Tx scaling and Rx coarse CFO correction blocks) instead of DSP48's. The V2Pro version of the PHY uses too many multipliers for the V4FX100 FPGA, but the V4 FPGA has more than enough logic to realize the extra multiplications in fabric.

Download the full XPS projects:

Both projects were built using the latest versions of the 10.1 release of the Xilinx tools (ISE 10.1.03 + IP3, EDK 10.1.03, Sysgen 10.1.3.1386).

Hardware Changes

  • Rebuilt the Tx pilot insertion logic, to interleave pilots in time and space for Alamouti mode.
  • Rebuilt the Rx phase estimation and tracking systems to improve phase error and CFO performance.
  • Rebuilt the Rx correlator to improve packet detection performance, especially in Alamouti mode with two Tx antennas
  • Fixed random payload generator (it previously results in invalid checksums)
  • Added random payload capture logic, to write random payloads to a packet buffer for offloading via Ethernet for BER processing
  • Built a real CRC-16 calculator for the header checksums (reduces chances of checksum collisions)
  • Fixed bug in AGC core, which (very rarely) resulted in bogus DC offset correction values being applied for many packets in a row
  • Upgraded to clock_board_config_v1_05_a, adding support for run-time selection of local or off board clock sources.

Software Changes

  • Added support for the WARPnet Measurement Framework, including a new top-level application (WARPNET_EXAMPLE).
  • Updated warpphy/warpmac to reflect changes to registers in the PHY.

Using the Design

  • Same as v14.0 (see below).

Previous Releases