Changes between Version 5 and Version 6 of SimpleStreamingReferenceDesign
- Timestamp:
- Aug 5, 2008, 5:50:57 PM (16 years ago)
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SimpleStreamingReferenceDesign
v5 v6 11 11 == Using the Reference Design == 12 12 13 The design itself contains both a transmitter and a receiver. By default, the transmit mode is configured if the design is downloaded to a board with the FPGA board's dip switch set to zero (all four bits to the left). The receive mode is configured if downloaded to a board with the FPGA board's dip switch set to one (top three bits to the left and the bottom bit to the right). If you have a wiki:HardwareUsersGuides/AnalogBoard_v1.1 WARP Analog Board] inserted into slot 4 of the FPGA board, the received constellation can be displayed on an oscilloscope that is capable of displaying the output of DAC1 vs. DAC2.13 The design itself contains both a transmitter and a receiver. By default, the transmit mode is configured if the design is downloaded to a board with the FPGA board's dip switch set to zero (all four bits to the left). The receive mode is configured if downloaded to a board with the FPGA board's dip switch set to one (top three bits to the left and the bottom bit to the right). If you have a [wiki:HardwareUsersGuides/AnalogBoard_v1.1 WARP Analog Board] inserted into slot 4 of the FPGA board, the received constellation can be displayed on an oscilloscope that is capable of displaying the output of DAC1 vs. DAC2. 14 14 15 15 == Download ==