wiki:SimpleStreamingReferenceDesign

Version 2 (modified by chunter, 16 years ago) (diff)

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Preliminary Release

Taken from http://warp.rice.edu/forums/viewtopic.php?pid=1307#p1307 :

The "simple streaming" PHY is the physical layer that students build when they take a wireless architecture class we offer here at Rice. This Fall will be the first time this class is taught on WARP, and so it's the first time that they will venture outside of the world of System Generator in order to test their designs.

We are nearly finished with the EDK project that includes the simple streaming peripheral and we will post it as an educational reference design that is analogous to the ofdm reference designs we already post. This will happen before classes start, so I'd expect it to be posted within a week or two. In the meantime, however, the underlying subsystems of the PHY each correspond to a lecture given in the course. Thus, the best documentation we have for the core right now is the course website itself: http://cmclab.rice.edu/433/.

I'll make sure to reply to this thread when the educational reference design goes online.

Preliminary Release: Simple Streaming Reference Design v00 (20MB .zip file)

Note: This is for kits with a 40MHz converter reference clock. Also, this project uses the latest Service Pack 2 version 10 Xilinx tools.