Changes between Version 8 and Version 9 of WARPLab/Debugging


Ignore:
Timestamp:
Sep 8, 2015, 5:06:41 PM (9 years ago)
Author:
welsh
Comment:

--

Legend:

Unmodified
Added
Removed
Modified

  • WARPLab/Debugging

    v8 v9  
    66
    77----
     8== ERROR:  Boot problems ==
     9
     10During the boot of a WARP node, the hex display and the LEDs provide information about the state of the boot process.  Here is a list of the various hex display / LED states to help debug boot issues:
     11
     12{{{#!td align=justify
     13Hex Display
     14}}}
     15{{{#!td 
     16LED State
     17}}}
     18{{{#!td
     19Boot State
     20}}}
     21|----------------
     22{{{#!td align=justify
     23OFF
     24}}}
     25{{{#!td 
     26OFF
     27}}}
     28{{{#!td
     29If power is on, then board is waiting for bitstream to be downloaded or bitstream is currently being downloaded to the board
     30}}}
     31|----------------
     32{{{#!td align=justify
     33{{{8.8.}}}
     34}}}
     35{{{#!td 
     36OFF
     37}}}
     38{{{#!td
     39If CM-MMCX or CM-PLL modules are present, then board is waiting for a valid reference clock.  You can confirm this by attaching the UART and looking for the following message:
     40{{{
     41***********************************************
     42     ***** WARP v3 Clock Config Core *****
     43      Program Assembly Date: 24 Jan 2015
     44
     45No config data in EEPROM - Using Defaults
     46Detected CM-PLL Module
     47Loading configuration B
     48Waiting for valid PLL ref clk......
     49}}}
     50To resolve this, either provide a valid clock or change the clock module settings.
     51}}}
     52|----------------
     53{{{#!td align=justify
     54{{{00}}}
     55}}}
     56{{{#!td 
     57OFF
     58}}}
     59{{{#!td
     60Boot of the node is proceeding.  Wait for a different condition.
     61}}}
     62|----------------
     63{{{#!td align=justify
     64{{{E0}}}
     65}}}
     66{{{#!td 
     67Red LEDs Flashing
     68}}}
     69{{{#!td
     70Right shift operator not working correctly.  This is an issue with the 14.7 Xilinx tools when using the {{{-Os}}} optimization.  Use the 14.4 Xilinx tools or use a different optimization level.
     71}}}
     72|----------------
     73{{{#!td align=justify
     74{{{E1}}}
     75}}}
     76{{{#!td 
     77Red LEDs Flashing
     78}}}
     79{{{#!td
     80Node initialization error.  This could be due to a mismatch between the hardware and software used in the bitstream or a failure of one of the hardware components.  Please see the UART output for more debug information.
     81}}}
     82|----------------
     83{{{#!td align=justify
     84{{{E2}}}
     85}}}
     86{{{#!td 
     87Red LEDs Flashing
     88}}}
     89{{{#!td
     90Sub-system initialization error.  This is generally due to an issue in the RF interfaces (for example an RF interface failed to lock or there is a mismatch between the number of RF interfaces on the board and the number specified by the bitstream) but could be caused by any of the Trigger Manager, Baseband, Interface, or User sub-systems.  Please see the UART output for more debug information.
     91}}}
     92|----------------
     93{{{#!td align=justify
     94{{{E3}}}
     95}}}
     96{{{#!td 
     97Red LEDs Flashing
     98}}}
     99{{{#!td
     100Transport initialization error.  Please see the UART output for more debug information.
     101}}}
     102|----------------
     103|----------------
     104{{{#!td align=justify
     105{{{E4}}}
     106}}}
     107{{{#!td 
     108Red LEDs Flashing
     109}}}
     110{{{#!td
     111Linker command file issue.  The linker command file does not place the global transport data structures into BRAM that is accessible by the DMA.  Please use the linker command file provided by the reference design and only make hand modifications to the linker command file to meet your project needs. 
     112}}}
     113|----------------
     114{{{#!td align=justify
     115{{{E5}}}
     116}}}
     117{{{#!td 
     118Red LEDs Flashing
     119}}}
     120{{{#!td
     121Interrupt initialization error.  Please see the UART output for more debug information.
     122}}}
     123|----------------
     124{{{#!td align=justify
     125{{{E6}}}
     126}}}
     127{{{#!td 
     128Red LEDs Flashing
     129}}}
     130{{{#!td
     131Interrupt enable error.  Please see the UART output for more debug information.
     132}}}
     133|----------------
     134{{{#!td align=justify
     135{{{01}}} to {{{99}}}
     136}}}
     137{{{#!td 
     138Green LED Flashing
     139}}}
     140{{{#!td
     141Waiting for a valid Ethernet connection.  UART output should be similar to:
     142{{{
     143WARPLab vX.Y.Z (compiled Sep  1 2015 15:29:29)
     144Configured for 2 RF Interfaces - Using WARP v3 on-board RF interfaces
     145No clock module detected - selecting on-board clocks
     146
     147NODE: W3-a-AAAAA using Node ID: 1
     148DRAM SODIMM detected ...
     149  Contents not cleared
     150Configuring baseband ...
     151  Using DDR for buffers
     152  Rx samples:       32768 ( 134217728 max)
     153  Tx samples:       32768 ( 117440512 max)
     154Configuring transport ...
     155  ETH A MAC Address: 40:D8:55:NN:NN:NN
     156  ETH A IP  Address: 10.0.0.2
     157  Configuring ETH A with 9024 byte buffers (2 receive, 2 send)
     158  ETH A speed 1000 Mbps (default)
     159  Listening on UDP ports 9000 (unicast) and 10000 (broadcast)
     160
     161Waiting for Ethernet link ...
     162}}}
     163where X.Y.Z shows your WARPLab version; AAAAA is your hardware serial number; and NN:NN:NN are the last six digits of your MAC address.
     164}}}
     165|----------------
     166
     167
     168A successful boot will have the Hex display indicate the last octet of the IP address of the node and the green LEDs will be used to indicate that valid WARPLab commands / packets are being received by the node.  The UART output will be:
     169
     170{{{
     171WARPLab vX.Y.Z (compiled Sep  1 2015 15:29:29)
     172Configured for 2 RF Interfaces - Using WARP v3 on-board RF interfaces
     173No clock module detected - selecting on-board clocks
     174
     175NODE: W3-a-AAAAA using Node ID: 1
     176DRAM SODIMM detected ...
     177  Contents not cleared
     178Configuring baseband ...
     179  Using DDR for buffers
     180  Rx samples:       32768 ( 134217728 max)
     181  Tx samples:       32768 ( 117440512 max)
     182Configuring transport ...
     183  ETH A MAC Address: 40:D8:55:NN:NN:NN
     184  ETH A IP  Address: 10.0.0.2
     185  Configuring ETH A with 9024 byte buffers (2 receive, 2 send)
     186  ETH A speed 1000 Mbps (default)
     187  Listening on UDP ports 9000 (unicast) and 10000 (broadcast)
     188
     189Waiting for Ethernet link ...
     190
     191Initialization Successful - Waiting for Commands from MATLAB
     192}}}
     193where X.Y.Z shows your WARPLab version; AAAAA is your hardware serial number; and NN:NN:NN are the last six digits of your MAC address.
     194
     195 
     196
     197
     198
     199----
     200== ERROR:  Maximum number of transmissions ==
    8201{{{
    9202Error using wl_transport_eth_udp_pnet/send (line 228)
    … …  
    43236
    44237----
     238== ERROR:  Broadcast Triggers ==
    45239
    46240{{{
    … …  
    64258
    65259----
     260== ERROR:  DMA transfers ==
     261
    66262If you make changes to the WARPLab software project, you may see this error printed via the UART:
    67263{{{
    … …  
    73269
    74270To resolve this error update your linker script to assign data sections to a memory area accessible by the AXI interconnect. The axi_bram (listed as {{{axi_bram_0_S_AXI_BASEADDR}}} in the current design) is a good choice.
     271
     272----
     273
     274