| | 10 | |
| | 11 | == 7.5.0 Release: == |
| | 12 | '''Download: [http://warpproject.org/dl/refdes/warplab/v7/release/WARPLab_Reference_Design_7.5.0.zip WARPLab_Reference_Design_7.5.0.zip]''' |
| | 13 | |
| | 14 | * '''Requires use of WARPXilnet library 3.03.a''' - [wiki:edk_user_repository update your edk_user_repository] before compiling the reference software project |
| | 15 | |
| | 16 | WARPLab 7.5 for WARP v3 adds support for storing Tx/Rx samples in the on-board 2GB DRAM. Using the DRAM enables Tx and Rx waveforms with more than 1000x the number of samples as previous WARPLab releases. See the [wiki:../LargeBuffers large buffers] page for details on the new waveform length limits. |
| | 17 | |
| | 18 | Other changes: |
| | 19 | |
| | 20 | * Replaced the old WARPLab AGC core with a new core derived from the wlan_agc core in the 802.11 Reference Design. The System Generator model for the new core is available in the repository: [browser:ResearchApps/PHY/WARPLAB/WARPLab7/Sysgen_Reference/w3/warplab_agc_v3 warplab_agc_v3]. |
| | 21 | * Added new spectrogram Rx example ([browser:ResearchApps/PHY/WARPLAB/WARPLab7/M_Code_Examples/wl_example_siso_spectrogram.m wl_example_siso_spectrogram.m]) |
| | 22 | * Updated all other examples to adopt new conventions for setting Tx/Rx waveform lengths |
| | 23 | * Added support for receiving Ethernet triggers on ETH B on WARP v3 hardware |
| | 24 | * Tweaked mex auto-compilation code to not require specific version of Microsoft tools |
| | 25 | * Updated mapping of debug pins - see the WARPLab [wiki:../HardwareConfiguration/WARPv3 WARP v3 hardware] usage for details |
| | 26 | * Added support for the CM-PLL clock module |
| | 27 | * Upgraded to the latest [wiki:cores/w3_clock_controller w3_clock_controller_axi] core |
| | 28 | * WARPLab assumes you have not written custom clock configurations to the EEPROM (see [wiki:cores/w3_clock_controller#Pre-BootConfiguration w3_clock_controller]). If you have customized the clock configurations in the EEPROM be sure to update {{{node_clk_initialize()}}} in [browser:/ResearchApps/PHY/WARPLAB/WARPLab7/C_Code_Reference/wl_node.c#L544 wl_node.c] to match. |
| | 29 | * '''NOTE:''' the updated core changes the interpretation of the clock module switches! See the WARPLab [wiki:../HardwareConfiguration/WARPv3 WARP v3 hardware] usage page for details on the new interpretation of the CM-PLL and CM-MMCX switches. |
| | 30 | * Added trigger inputs/outputs for the CM-PLL board-to-board cables. The 4 inputs and 4 outputs mirror the corresponding trigger signals on the debug header. |
| | 31 | |
| | 32 | ---- |
| | 33 | |
| | 34 | Release Details: |
| | 35 | ||= Hardware =||= Release =||= Date Posted =||= SVN Rev. =||= ISE Ver. =||= Arch =||= MATLAB Ver. =||= RF Interface Support =|| |
| | 36 | || WARP v3 || 7.5.0 || 25-Feb-2014 || [browser:ResearchApps/PHY/WARPLAB/WARPLab7?rev=XXX XXX] || 14.4 || MB/AXI || 2009b or later || 1-2: WARP v3 on-board interfaces [[BR]] 3-4: Requires [wiki:HardwareUsersGuides/FMC-RF-2X245 FMC-RF-2X245] || |
| | 37 | || WARP v2 || 7.5.0 |||||||||||||| Coming Soon || |
| | 38 | |
| | 39 | |
