wiki:WARPLab/Downloads

Version 70 (modified by welsh, 9 years ago) (diff)

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WARPLab Reference Design: Downloads

The latest WARPLab Reference Design is available for download below. The source and binary files are distributed under the terms of the WARP License.

Previous releases of the reference design are available in the WARPLab change log.

Refer to the Quick Start guide to get started with the reference design.

7.5.1 Release:

Download: WARPLab_Reference_Design_7.5.1.zip

Release Details:

Hardware Release Date Posted SVN Rev. ISE Ver. Arch MATLAB Ver. RF Interface Support
WARP v3 7.5.1 12-Mar-2015 4487 14.4 MB/AXI 2009b or later 1-2: WARP v3 on-board interfaces
3-4: Requires FMC-RF-2X245
WARP v2 7.5.1 12-Mar-2015 4487 14.4 PPC/PLB 2009b or later 1-2: Radios in slots 2 & 3
3-4: Radios in slots 1 & 4

WARPLab 7.5.1 for WARP v2 aligns the WARP v2 peripherals with the WARPLab 7.5.0 WARP v3 peripherals.

  • Updated the Porting Guide with new scripting conventions. In 7.5, these changes are optional so old scripts will work as-is. In future releases, these changes will be enforced.
  • Replaced the old WARPLab AGC core with a new core derived from the wlan_agc core in the 802.11 Reference Design. The System Generator model for the new core is available in the repository: warplab_agc_v3.
  • Updated to version 3.04.a of the WARPxilnet library - be sure to update your edk_user_repository before compiling the reference software project
    • NOTE: When rebuilding the BSP with the WARPxilnet library, in the Board Support Package Settings, the "ETH_B_uses_xilnet" should be set to zero (0) under the WARPxilnet settings since WARP v2 does not have a second Ethernet port.
  • Updated mapping of debug pins - see the WARPLab WARP v2 hardware usage for details

WARPLab 7.5.1 for WARP v3 provides transport improvements to the existing WARPLab 7.5.0 design.

Other changes:

  • Updated the radio controller core - be sure to update your edk_user_repository before compiling the reference software project
  • Updated the Tigger Manager to split Ethernet and SW triggers. The SW trigger is not used by the reference design and is dedicated for use by custom user C code.
  • Updated MEX transport (see Benchmarks) - WARPLab 7.5.x requires MEX 1.0.2a
    • Improved Write IQ performance
    • Removed performance penalty when calling 'read_IQ' / 'write_IQ' with multiple buffers (ie when the transport had to iterate over multiple buffers in one call)
  • Updated Java transport (see Benchmarks)
    • Improved Write IQ performance
    • Improved Read IQ performance and removed performance issue for larger buffers
  • Added ability to auto-negotiate the Ethernet link speed. This feature is disabled by default because it added 1 to 2 seconds for the node to boot. To enable the feature, change the WL_NEGOTIATE_ETH_LINK_SPEED define to 1 in node.c
  • Implemented fix for AXI Ethernet v3.01.a bug detailed in Xilinx AR# 56158. If rebuilding, the WARP v3 XPS project, it is suggested that users patch the AXI Ethernet core in their installation. The diff of the changes in the Ethernet core are:
    $ diff axi_ethernet_v3_01_a_v6_rx_axi_intf.v axi_ethernet_v3_01_a_v6_rx_axi_intf.orig
    155c155
    <       if ((rx_good_frame | rx_bad_frame) && (rx_state != IDLE)) begin
    ---
    >       if (rx_good_frame | rx_bad_frame) begin
    
  • Cleaned up the code split between WARP v3 and WARP v2 hardware within the C code
  • Cleaned up code examples and added more comments

7.5.0 Release:

Download: WARPLab_Reference_Design_7.5.0.zip

Release Details:

Hardware Release Date Posted SVN Rev. ISE Ver. Arch MATLAB Ver. RF Interface Support
WARP v3 7.5.0 11-Feb-2015 4388 14.4 MB/AXI 2009b or later 1-2: WARP v3 on-board interfaces
3-4: Requires FMC-RF-2X245
WARP v2 7.5.0 Coming Soon

WARPLab 7.5 for WARP v3 adds support for storing Tx/Rx samples in the on-board 2GB DRAM. Using the DRAM enables Tx and Rx waveforms with more than 1000x the number of samples as previous WARPLab releases. See the Sample Buffer Sizes page for details on the new waveform length limits.

We extend our thanks to Matthias Schulz at TU Darmstadt for sharing results from his early exploration of a DRAM-enabled WARPLab design. The success of this approach in his application provided the impetus for re-designing the WARPLab FPGA architecture to support DRAM-backed sample buffers for all RF interfaces in the official reference design.

Other changes:

  • Updated the Porting Guide with new scripting conventions. In 7.5, these changes are optional so old scripts will work as-is. In future releases, these changes will be enforced.
  • Updates to the FPGA Architecture.
  • Replaced the old WARPLab AGC core with a new core derived from the wlan_agc core in the 802.11 Reference Design. The System Generator model for the new core is available in the repository: warplab_agc_v3.
  • Updated to version 3.04.a of the WARPXilnet library - be sure to update your edk_user_repository before compiling the reference software project
  • Added new spectrogram Rx example (WARPLab Spectrogram Example)
  • Updated all other examples to adopt new conventions for setting Tx/Rx waveform lengths
  • Added support for receiving Ethernet triggers on ETH B on WARP v3 hardware
  • Tweaked mex auto-compilation code to not require specific version of Microsoft tools
  • Updated mapping of debug pins - see the WARPLab WARP v3 hardware usage for details
  • Added support for the CM-PLL clock module
  • Upgraded to the latest w3_clock_controller_axi core
    • WARPLab assumes you have not written custom clock configurations to the EEPROM (see w3_clock_controller). If you have customized the clock configurations in the EEPROM be sure to update node_clk_initialize() in wl_node.c to match.
    • NOTE: the updated core changes the interpretation of the clock module switches! See the WARPLab WARP v3 hardware usage page for details on the new interpretation of the CM-PLL and CM-MMCX switches.
  • Added trigger inputs/outputs for the CM-PLL board-to-board cables. The 4 inputs and 4 outputs mirror the corresponding trigger signals on the debug header.
  • Updated all examples to explicitly configure trigger inputs/outputs. User scripts should mimic this approach of not relying on the at-boot default trigger configurations.

Reference Design Archive

The WARPLab reference design is packaged as a .zip file with the full source code and compiled bitstreams for the reference design. You can view the latest source code in the repository (ResearchApps/PHY/WARPLAB/WARPLab7). Please note the code in the repository is under active development.

The contents of the WARPLab reference design .zip file are explained below.

Bitstreams_Reference

Bitstreams are fully-built designs that are ready to be downloaded onto WARP hardware. Files ending with the extension '.bit' may be downloaded using the Xilinx tool iMPACT. Files ending with the extension .bin may loaded onto an SD card so that the WARP v3 hardware will automatically be programmed whenever it is powered on and has the SD card inserted. Details on how to configure an SD card with a '.bin' file are provided here. For WARP v2 hardware, compact flash cards may be loaded with the provided .ace files for similar functionality (instructions provided here).

  • w3: WARP v3 FPGA bitstreams (see SD config howto for help using the .bin file)
  • w2: WARP v2 FPGA bitstreams (see CF config howto for help using the .ace file)

EDK_Projects

This folder contains EDK projects for various hardware configurations. The WARPLab FPGA design is built with the Xilinx Embedded Development Kit (EDK) software. The hardware design is constructed and implemented in EDK Xilinx Platform Studio (XPS). The software design, running in the MicroBlaze processor, is built in the Xilinx SDK. Opening these EDK projects requires a copy of the WARP edk_user_repository at the SVN revision in the table above.

If you want to use (but not modify) the reference FPGA design, you only need a bitstream and the reference M code. If you want to modify the MicroBlaze/PPC C code, you can download an EDK project in this folder, but only modify the SDK project contained therein. To modify the FPGA hardware design, you will need to modify the XPS project. The WARPLab FPGA design uses custom peripherals designed in Xilinx System Generator, including the warplab_buffers core. You will need MATLAB, Simulink and System Generator to modify these cores.

Each of these EDK projects are a combination of an XPS project along with Eclipse software projects that can be imported into an SDK workspace. These software projects are present in the 'SDK_Workspace' subfolder of every XPS project -- we recommend using this folder as the location of the SDK Workspace. These projects can then be imported "in place" and will not need to be copied.

  • w3: WARP v3 EDK projects for the 2-radio (2RF) and 4-radio (4RF) WARPLab Reference Designs
  • w2: WARP v2 EDK projects for the 2-radio (2RF) and 4-radio (4RF) WARPLab Reference Designs

M_Code_Examples

This folder contains example WARPLab scripts that are compatible with this release of WARPLab. Explanations of these scripts are available here.

M_Code_Reference

This folder contains all of the supporting files needed for WARPLab to run on a host PC with MATLAB. When downloading a new Reference Design Release, users will need to run the wl_setup.m script in this folder.