| 19 | |
| 20 | Please review the XPS project for the latest information. |
| 21 | |
| 22 | |
| 23 | === Microblaze Address Map === |
| 24 | |
| 25 | '''NOTE: All Address not explicitly defined are reserved.''' |
| 26 | |
| 27 | ||= '''IP Instance''' =||= '''Base Address''' =||= '''High Address''' =||= '''Size''' =|| |
| 28 | || DLMB || 0x0000_0000 || 0x0001_FFFF || 128K || |
| 29 | || ILMB || 0x0000_0000 || 0x0001_FFFF || 128K || |
| 30 | || Debug || 0x4000_0000 || 0x4000_FFFF || 64K || |
| 31 | || AXI GPIO || 0x4010_0000 || 0x4010_FFFF || 64K || |
| 32 | || AXI Timer || 0x4080_0000 || 0x4080_FFFF || 64K || |
| 33 | || USB UART || 0x4100_0000 || 0x4100_FFFF || 64K || |
| 34 | || AXI SYSMON ADC || 0x4180_0000 || 0x4180_FFFF || 64K || |
| 35 | || W3 I2C EEPROM On Board || 0x4200_0000 || 0x4200_FFFF || 64K || |
| 36 | || W3 I2C EEPROM FMC || 0x4201_0000 || 0x4201_FFFF || 64K || |
| 37 | || W3 Clock Controller || 0x5000_0000 || 0x5000_FFFF || 64K || |
| 38 | || W3 User IO || 0x5100_0000 || 0x5100_FFFF || 64K || |
| 39 | || WARPLab AGC || 0x5180_0000 || 0x5180_FFFF || 64K || |
| 40 | || Radio Controller || 0x5200_0000 || 0x5200_FFFF || 64K || |
| 41 | || W3 AD Controller || 0x5280_0000 || 0x5280_FFFF || 64K || |
| 42 | || WARPLab Trigger Proc || 0x5300_0000 || 0x5300_FFFF || 64K || |
| 43 | || ETH A MAC || 0x7000_0000 || 0x7003_FFFF || 256K || |
| 44 | || ETH B MAC || 0x7010_0000 || 0x7013_FFFF || 256K || |
| 45 | || AXI DMA (ETH A) || 0x7020_0000 || 0x7020_FFFF || 64K || |
| 46 | || Ethernet FIFO (ETH B) || 0x7030_0000 || 0x7030_FFFF || 64K || |
| 47 | || CDMA || 0x7200_0000 || 0x7200_FFFF || 64K || |
| 48 | || WARPLab Buffers || 0x7800_0000 || 0x787F_FFFF || 8M || |
| 49 | || BRAM || 0x8000_0000 || 0x8001_FFFF || 128K || |
| 50 | || DDR || 0xC000_0000 || 0xFFFF_FFFF || 1G || |