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= WARPLab 7.3.0 FPGA Architecture for WARP v3 Hardware =

The WARPLab 7.3.0 design for WARP v3 makes changes to the underlying FPGA architecture in order to improve performance for Read / Write IQ.  This includes:

  * Updates to the WARPLab Buffers core to move the Read / Write IQ memories out to the AXI interconnect
  * Updates to the AXI Interconnect to allow DMA access to all the WARPLab Buffers

== Interconnect Architecture ==

[[Image(WARPLab_7_3_0_interconnect_architecture.png)]]


== Address Map ==