Changes between Version 49 and Version 50 of WARPLab6/Changelog


Ignore:
Timestamp:
Sep 10, 2012, 9:32:12 AM (12 years ago)
Author:
chunter
Comment:

--

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  • WARPLab6/Changelog

    v49 v50  
    1313== '''Notes for v6.1''' ==
    1414||= Hardware =||= Release =||= Date Posted =||= ISE Ver =||= 2 Radio Download =||= 4 Radio Download =||
    15 ||  WARP v2  ||  6.2  ||  Jul-2012  ||  13.4  ||  [export:/ResearchApps/PHY/WARPLAB/WARPLab_v06_1/Bitstreams/WARPLab_2x2_v06_01_FPGAv2.bit?rev=1761 WARPLab_2x2_v06_01_FPGAv2.bit][[BR]] [export:/ResearchApps/PHY/WARPLAB/WARPLab_v06_1/ACE_Files/WARPLab_2x2_v06_01_FPGAv2.ace?rev=1761 WARPLab_2x2_v06_01_FPGAv2.ace][[BR]] [http://warp.rice.edu/bigFiles/WARPLab_ReferenceDesign_2x2_v06_01_FPGAv2.zip WARPLab_ReferenceDesign_2x2_v06_01_FPGAv2.zip]  ||  [export:/ResearchApps/PHY/WARPLAB/WARPLab_v06_1/Bitstreams/WARPLab_4x4_v06_01_FPGAv2.bit?rev=1761 WARPLab_4x4_v06_01_FPGAv2.bit][[BR]][export:/ResearchApps/PHY/WARPLAB/WARPLab_v06_1/ACE_Files/WARPLab_4x4_v06_01_FPGAv2.ace?rev=1761 WARPLab_4x4_v06_01_FPGAv2.ace][[BR]] [http://warp.rice.edu/bigFiles/WARPLab_ReferenceDesign_4x4_v06_01_FPGAv2.zip WARPLab_ReferenceDesign_4x4_v06_01_FPGAv2.zip]  ||
    16 ||  WARP v1  ||  6.2  ||  Jul-2012  ||  10.1.03  ||  [export:/ResearchApps/PHY/WARPLAB/WARPLab_v06_1/Bitstreams/WARPLab_2x2_v06_01_FPGAv1.bit?rev=1761 WARPLab_2x2_v06_01_FPGAv1.bit][[BR]] [export:/ResearchApps/PHY/WARPLAB/WARPLab_v06_1/ACE_Files/WARPLab_2x2_v06_01_FPGAv1.ace?rev=1761 WARPLab_2x2_v06_01_FPGAv1.ace][[BR]] [http://warp.rice.edu/bigFiles/WARPLab_ReferenceDesign_2x2_v06_01_FPGAv1.zip WARPLab_ReferenceDesign_2x2_v06_01_FPGAv1.zip]  ||  [export:/ResearchApps/PHY/WARPLAB/WARPLab_v06_1/Bitstreams/WARPLab_4x4_v06_01_FPGAv1.bit?rev=1761 WARPLab_4x4_v06_01_FPGAv1.bit][[BR]][export:/ResearchApps/PHY/WARPLAB/WARPLab_v06_1/ACE_Files/WARPLab_4x4_v06_01_FPGAv1.ace?rev=1761 WARPLab_4x4_v06_01_FPGAv1.ace][[BR]] [http://warp.rice.edu/bigFiles/WARPLab_ReferenceDesign_4x4_v06_01_FPGAv1.zip WARPLab_ReferenceDesign_4x4_v06_01_FPGAv1.zip]  ||
     15||  WARP v2  ||  6.1  ||  Jul-2012  ||  13.4  ||  [export:/ResearchApps/PHY/WARPLAB/WARPLab_v06_1/Bitstreams/WARPLab_2x2_v06_01_FPGAv2.bit?rev=1761 WARPLab_2x2_v06_01_FPGAv2.bit][[BR]] [export:/ResearchApps/PHY/WARPLAB/WARPLab_v06_1/ACE_Files/WARPLab_2x2_v06_01_FPGAv2.ace?rev=1761 WARPLab_2x2_v06_01_FPGAv2.ace][[BR]] [http://warp.rice.edu/bigFiles/WARPLab_ReferenceDesign_2x2_v06_01_FPGAv2.zip WARPLab_ReferenceDesign_2x2_v06_01_FPGAv2.zip]  ||  [export:/ResearchApps/PHY/WARPLAB/WARPLab_v06_1/Bitstreams/WARPLab_4x4_v06_01_FPGAv2.bit?rev=1761 WARPLab_4x4_v06_01_FPGAv2.bit][[BR]][export:/ResearchApps/PHY/WARPLAB/WARPLab_v06_1/ACE_Files/WARPLab_4x4_v06_01_FPGAv2.ace?rev=1761 WARPLab_4x4_v06_01_FPGAv2.ace][[BR]] [http://warp.rice.edu/bigFiles/WARPLab_ReferenceDesign_4x4_v06_01_FPGAv2.zip WARPLab_ReferenceDesign_4x4_v06_01_FPGAv2.zip]  ||
     16||  WARP v1  ||  6.1  ||  Jul-2012  ||  10.1.03  ||  [export:/ResearchApps/PHY/WARPLAB/WARPLab_v06_1/Bitstreams/WARPLab_2x2_v06_01_FPGAv1.bit?rev=1761 WARPLab_2x2_v06_01_FPGAv1.bit][[BR]] [export:/ResearchApps/PHY/WARPLAB/WARPLab_v06_1/ACE_Files/WARPLab_2x2_v06_01_FPGAv1.ace?rev=1761 WARPLab_2x2_v06_01_FPGAv1.ace][[BR]] [http://warp.rice.edu/bigFiles/WARPLab_ReferenceDesign_2x2_v06_01_FPGAv1.zip WARPLab_ReferenceDesign_2x2_v06_01_FPGAv1.zip]  ||  [export:/ResearchApps/PHY/WARPLAB/WARPLab_v06_1/Bitstreams/WARPLab_4x4_v06_01_FPGAv1.bit?rev=1761 WARPLab_4x4_v06_01_FPGAv1.bit][[BR]][export:/ResearchApps/PHY/WARPLAB/WARPLab_v06_1/ACE_Files/WARPLab_4x4_v06_01_FPGAv1.ace?rev=1761 WARPLab_4x4_v06_01_FPGAv1.ace][[BR]] [http://warp.rice.edu/bigFiles/WARPLab_ReferenceDesign_4x4_v06_01_FPGAv1.zip WARPLab_ReferenceDesign_4x4_v06_01_FPGAv1.zip]  ||
    1717
    1818* Small, but important, bug fix. MAC addresses for each node were not updated based on dip switch value. This made any setup larger than 1 node fail due to arp table collisions. This has been resolved. v6.0 is deprecated and should not be used
    19 == '''Notes for v6.0''' ''Posted July 2012'' ==
     19== '''Notes for v6.0''' ==
    2020||= Hardware =||= Release =||= Date Posted =||= ISE Ver =||= 2 Radio Download =||= 4 Radio Download =||
    2121||  WARP v2  ||  6.0  ||  Jul-2012  ||  13.4  ||  [http://warp.rice.edu/trac/export/1755/ResearchApps/PHY/WARPLAB/WARPLab_v06_0/Bitstreams/WARPLab_2x2_v06_00_FPGAv2.bit WARPLab_2x2_v06_00_FPGAv2.bit][[BR]] [export:/ResearchApps/PHY/WARPLAB/WARPLab_v06_0/ACE_Files/WARPLab_2x2_v06_00_FPGAv2.ace?rev=1755 WARPLab_2x2_v06_00_FPGAv2.ace][[BR]] [http://warp.rice.edu/bigFiles/WARPLab_ReferenceDesign_2x2_v06_00_FPGAv2.zip WARPLab_ReferenceDesign_2x2_v06_01_FPGAv2.zip]  ||  [http://warp.rice.edu/trac/export/1755/ResearchApps/PHY/WARPLAB/WARPLab_v06_0/Bitstreams/WARPLab_4x4_v06_00_FPGAv2.bit WARPLab_4x4_v06_00_FPGAv2.bit][[BR]][http://warp.rice.edu/trac/export/1755/ResearchApps/PHY/WARPLAB/WARPLab_v06_0/ACE_Files/WARPLab_4x4_v06_00_FPGAv2.ace WARPLab_4x4_v06_00_FPGAv2.ace][[BR]] [http://warp.rice.edu/bigFiles/WARPLab_ReferenceDesign_4x4_v06_00_FPGAv2.zip WARPLab_ReferenceDesign_4x4_v06_00_FPGAv2.zip]  ||
    22 ||  WARP v1  ||  6.0  ||  Jul-2012  ||  10.1.03  ||  [http://warp.rice.edu/trac/export/1755/ResearchApps/PHY/WARPLAB/WARPLab_v06_0/Bitstreams/WARPLab_2x2_v06_00_FPGAv1.bit WARPLab_2x2_v06_00_FPGAv1.bit][[BR]] [export:/ResearchApps/PHY/WARPLAB/WARPLab_v06_0/ACE_Files/WARPLab_2x2_v06_00_FPGAv1.ace?rev=1755 WARPLab_2x2_v06_00_FPGAv1.ace][[BR]] [http://warp.rice.edu/bigFiles/WARPLab_ReferenceDesign_2x2_v06_00_FPGAv1.zip WARPLab_ReferenceDesign_2x2_v06_01_FPGAv1.zip]  ||  [http://warp.rice.edu/trac/export/1755/ResearchApps/PHY/WARPLAB/WARPLab_v06_0/Bitstreams/WARPLab_4x4_v06_00_FPGAv1.bit WARPLab_4x4_v06_00_FPGAv1.bit][[BR]][http://warp.rice.edu/trac/export/1755/ResearchApps/PHY/WARPLAB/WARPLab_v06_0/ACE_Files/WARPLab_4x4_v06_00_FPGAv1.ace WARPLab_4x4_v06_00_FPGAv1.ace][[BR]] [http://warp.rice.edu/bigFiles/WARPLab_ReferenceDesign_4x4_v06_00_FPGAv1.zip WARPLab_ReferenceDesign_4x4_v06_00_FPGAv1.zip]  ||
     22||  WARP v1  ||  6.0  ||  Jul-2012  ||  10.1.03  ||  [http://warp.rice.edu/trac/export/1755/ResearchApps/PHY/WARPLAB/WARPLab_v06_0/Bitstreams/WARPLab_2x2_v06_00_FPGAv1.bit WARPLab_2x2_v06_00_FPGAv1.bit][[BR]] [http://warp.rice.edu/trac/export/1755/ResearchApps/PHY/WARPLAB/WARPLab_v06_0/ACE_Files/WARPLab_2x2_v06_00_FPGAv1.ace WARPLab_2x2_v06_00_FPGAv1.ace][[BR]] [http://warp.rice.edu/bigFiles/WARPLab_ReferenceDesign_2x2_v06_00_FPGAv1.zip WARPLab_ReferenceDesign_2x2_v06_01_FPGAv1.zip]  ||  [http://warp.rice.edu/trac/export/1755/ResearchApps/PHY/WARPLAB/WARPLab_v06_0/Bitstreams/WARPLab_4x4_v06_00_FPGAv1.bit WARPLab_4x4_v06_00_FPGAv1.bit][[BR]][http://warp.rice.edu/trac/export/1755/ResearchApps/PHY/WARPLAB/WARPLab_v06_0/ACE_Files/WARPLab_4x4_v06_00_FPGAv1.ace WARPLab_4x4_v06_00_FPGAv1.ace][[BR]] [http://warp.rice.edu/bigFiles/WARPLab_ReferenceDesign_4x4_v06_00_FPGAv1.zip WARPLab_ReferenceDesign_4x4_v06_00_FPGAv1.zip]  ||
    2323
    24 WARP v2 EDK Download: [http://warp.rice.edu/bigFiles/WARPLab_ReferenceDesign_2x2_v06_00_FPGAv2.zip 2 Radio],[http://warp.rice.edu/bigFiles/WARPLab_ReferenceDesign_4x4_v06_00_FPGAv2.zip 4 Radio]
    25 
    26 WARP v1 EDK Download: [http://warp.rice.edu/bigFiles/WARPLab_ReferenceDesign_2x2_v06_00_FPGAv1.zip 2 Radio],[http://warp.rice.edu/bigFiles/WARPLab_ReferenceDesign_4x4_v06_00_FPGAv1.zip 4 Radio]
    2724* Design defaults to using gigabit Ethernet on WARP v2 Hardware (Virtex-4)
    2825* Improved packet handling on WARP v2 for fewer packet drops
    … …  
    3128* Thanks to a modified pnet for Matlab's UDP handling, WARPLab is sped by ~10x
    3229== '''Notes for v5.2''' ''Posted December 2009'' ==
    33 WARP v2 EDK Download: [http://warp.rice.edu/bigFiles/WARPLab_ReferenceDesign_2x2_v05_02_FPGAv2.zip 2 Radio],[http://warp.rice.edu/bigFiles/WARPLab_ReferenceDesign_4x4_v05_02_FPGAv2.zip 4 Radio]
     30||= Hardware =||= Release =||= Date Posted =||= ISE Ver =||= 2 Radio Download =||= 4 Radio Download =||
     31||  WARP v2  ||  5.2  ||  Dec-2009  ||  10.1.03  ||  [http://warp.rice.edu/trac/export/1442/ResearchApps/PHY/WARPLAB/WARPLab_v05_2/Bitstreams/WARPLab_2x2_v05_02_FPGAv2.bit WARPLab_2x2_v05_02_FPGAv2.bit][[BR]] [http://warp.rice.edu/trac/export/1442/ResearchApps/PHY/WARPLAB/WARPLab_v05_2/ACE_Files/WARPLab_2x2_v05_02_FPGAv2.ace WARPLab_2x2_v05_02_FPGAv2.ace][[BR]] [http://warp.rice.edu/bigFiles/WARPLab_ReferenceDesign_2x2_v05_02_FPGAv2.zip WARPLab_ReferenceDesign_2x2_v05_02_FPGAv2.zip]  ||  [http://warp.rice.edu/trac/export/1442/ResearchApps/PHY/WARPLAB/WARPLab_v05_2/Bitstreams/WARPLab_4x4_v05_02_FPGAv2.bit WARPLab_4x4_v05_02_FPGAv2.bit][[BR]][http://warp.rice.edu/trac/export/1442/ResearchApps/PHY/WARPLAB/WARPLab_v05_2/ACE_Files/WARPLab_4x4_v05_02_FPGAv2.ace WARPLab_4x4_v05_02_FPGAv2.ace][[BR]] [http://warp.rice.edu/bigFiles/WARPLab_ReferenceDesign_4x4_v05_02_FPGAv2.zip WARPLab_ReferenceDesign_4x4_v05_02_FPGAv2.zip]  ||
     32||  WARP v1  ||  5.2  ||  Dec-2009  ||  10.1.03  ||  [http://warp.rice.edu/trac/export/1442/ResearchApps/PHY/WARPLAB/WARPLab_v05_2/Bitstreams/WARPLab_2x2_v05_02_FPGAv1.bit WARPLab_2x2_v05_02_FPGAv1.bit][[BR]] [http://warp.rice.edu/trac/export/1442/ResearchApps/PHY/WARPLAB/WARPLab_v05_2/ACE_Files/WARPLab_2x2_v05_02_FPGAv1.ace WARPLab_2x2_v05_02_FPGAv1.ace][[BR]] [http://warp.rice.edu/bigFiles/WARPLab_ReferenceDesign_2x2_v05_02_FPGAv1.zip WARPLab_ReferenceDesign_2x2_v05_02_FPGAv1.zip]  ||  [http://warp.rice.edu/trac/export/1442/ResearchApps/PHY/WARPLAB/WARPLab_v05_2/Bitstreams/WARPLab_4x4_v05_02_FPGAv1.bit WARPLab_4x4_v05_02_FPGAv1.bit][[BR]][http://warp.rice.edu/trac/export/1442/ResearchApps/PHY/WARPLAB/WARPLab_v05_2/ACE_Files/WARPLab_4x4_v05_02_FPGAv1.ace WARPLab_4x4_v05_02_FPGAv1.ace][[BR]] [http://warp.rice.edu/bigFiles/WARPLab_ReferenceDesign_4x4_v05_02_FPGAv1.zip WARPLab_ReferenceDesign_4x4_v05_02_FPGAv1.zip]  ||
    3433
    35 WARP v1 EDK Download: [http://warp.rice.edu/bigFiles/WARPLab_ReferenceDesign_2x2_v05_02_FPGAv1.zip 2 Radio],[http://warp.rice.edu/bigFiles/WARPLab_ReferenceDesign_4x4_v05_02_FPGAv1.zip 4 Radio]
    3634* Can store RSSI data in the 4x4 design
    3735* Consolidated the Sysgen models. Now there is one Sysgen model, {{{warplab_mimo_4x4.mdl}}}, that implements the full system: 4 radios with I/Q and RSSI buffers. The 2x2 MIMO and 4x4 MIMO [wiki:WARPLab/RefDesign Reference Designs] are identical except the 2x2 Design leaves two paths of the model unconnected.