Changes between Version 50 and Version 51 of WARPLab6/Changelog


Ignore:
Timestamp:
Sep 10, 2012, 10:11:52 AM (12 years ago)
Author:
chunter
Comment:

--

Legend:

Unmodified
Added
Removed
Modified

  • WARPLab6/Changelog

    v50 v51  
    2727* Small change to M-code reference to reduce likelihood of "failed to receive ACK" error.
    2828* Thanks to a modified pnet for Matlab's UDP handling, WARPLab is sped by ~10x
    29 == '''Notes for v5.2''' ''Posted December 2009'' ==
     29== '''Notes for v5.2''' ==
    3030||= Hardware =||= Release =||= Date Posted =||= ISE Ver =||= 2 Radio Download =||= 4 Radio Download =||
    3131||  WARP v2  ||  5.2  ||  Dec-2009  ||  10.1.03  ||  [http://warp.rice.edu/trac/export/1442/ResearchApps/PHY/WARPLAB/WARPLab_v05_2/Bitstreams/WARPLab_2x2_v05_02_FPGAv2.bit WARPLab_2x2_v05_02_FPGAv2.bit][[BR]] [http://warp.rice.edu/trac/export/1442/ResearchApps/PHY/WARPLAB/WARPLab_v05_2/ACE_Files/WARPLab_2x2_v05_02_FPGAv2.ace WARPLab_2x2_v05_02_FPGAv2.ace][[BR]] [http://warp.rice.edu/bigFiles/WARPLab_ReferenceDesign_2x2_v05_02_FPGAv2.zip WARPLab_ReferenceDesign_2x2_v05_02_FPGAv2.zip]  ||  [http://warp.rice.edu/trac/export/1442/ResearchApps/PHY/WARPLAB/WARPLab_v05_2/Bitstreams/WARPLab_4x4_v05_02_FPGAv2.bit WARPLab_4x4_v05_02_FPGAv2.bit][[BR]][http://warp.rice.edu/trac/export/1442/ResearchApps/PHY/WARPLAB/WARPLab_v05_2/ACE_Files/WARPLab_4x4_v05_02_FPGAv2.ace WARPLab_4x4_v05_02_FPGAv2.ace][[BR]] [http://warp.rice.edu/bigFiles/WARPLab_ReferenceDesign_4x4_v05_02_FPGAv2.zip WARPLab_ReferenceDesign_4x4_v05_02_FPGAv2.zip]  ||
    … …  
    3535* Consolidated the Sysgen models. Now there is one Sysgen model, {{{warplab_mimo_4x4.mdl}}}, that implements the full system: 4 radios with I/Q and RSSI buffers. The 2x2 MIMO and 4x4 MIMO [wiki:WARPLab/RefDesign Reference Designs] are identical except the 2x2 Design leaves two paths of the model unconnected.
    3636* Minor update: Added the Null MGT wrapper core to the project (see note at the end of the [wiki:HardwareUsersGuides/FPGABoard_v2.2/MGTs FPGA Board user guide])
    37 == '''Notes for v5.1''' ''Posted November 2009'' ==
    38 WARP v2 EDK Download: [http://warp.rice.edu/bigFiles/WARPLab_ReferenceDesign_2x2_v05_01_FPGAv2.zip 2 Radio],[http://warp.rice.edu/bigFiles/WARPLab_ReferenceDesign_4x4_v05_01_FPGAv2.zip 4 Radio]
     37== '''Notes for v5.1''' ==
     38||= Hardware =||= Release =||= Date Posted =||= ISE Ver =||= 2 Radio Download =||= 4 Radio Download =||
     39||  WARP v2  ||  5.2  ||  Nov-2009  ||  10.1.03  ||  [http://warp.rice.edu/trac/export/1442/ResearchApps/PHY/WARPLAB/WARPLab_v05_1/Bitstreams/WARPLab_2x2_v05_01_FPGAv2.bit WARPLab_2x2_v05_01_FPGAv2.bit][[BR]] [http://warp.rice.edu/trac/export/1442/ResearchApps/PHY/WARPLAB/WARPLab_v05_1/ACE_Files/WARPLab_2x2_v05_01_FPGAv2.ace WARPLab_2x2_v05_01_FPGAv2.ace][[BR]] [http://warp.rice.edu/bigFiles/WARPLab_ReferenceDesign_2x2_v05_01_FPGAv2.zip WARPLab_ReferenceDesign_2x2_v05_01_FPGAv2.zip]  ||  [http://warp.rice.edu/trac/export/1442/ResearchApps/PHY/WARPLAB/WARPLab_v05_1/Bitstreams/WARPLab_4x4_v05_01_FPGAv2.bit WARPLab_4x4_v05_01_FPGAv2.bit][[BR]][http://warp.rice.edu/trac/export/1442/ResearchApps/PHY/WARPLAB/WARPLab_v05_1/ACE_Files/WARPLab_4x4_v05_01_FPGAv2.ace WARPLab_4x4_v05_01_FPGAv2.ace][[BR]] [http://warp.rice.edu/bigFiles/WARPLab_ReferenceDesign_4x4_v05_01_FPGAv2.zip WARPLab_ReferenceDesign_4x4_v05_01_FPGAv2.zip]  ||
     40||  WARP v1  ||  5.2  ||  Nov-2009  ||  10.1.03  ||  [http://warp.rice.edu/trac/export/1442/ResearchApps/PHY/WARPLAB/WARPLab_v05_1/Bitstreams/WARPLab_2x2_v05_01_FPGAv1.bit WARPLab_2x2_v05_01_FPGAv1.bit][[BR]] [http://warp.rice.edu/trac/export/1442/ResearchApps/PHY/WARPLAB/WARPLab_v05_1/ACE_Files/WARPLab_2x2_v05_01_FPGAv1.ace WARPLab_2x2_v05_01_FPGAv1.ace][[BR]] [http://warp.rice.edu/bigFiles/WARPLab_ReferenceDesign_2x2_v05_01_FPGAv1.zip WARPLab_ReferenceDesign_2x2_v05_01_FPGAv1.zip]  ||  [http://warp.rice.edu/trac/export/1442/ResearchApps/PHY/WARPLAB/WARPLab_v05_1/Bitstreams/WARPLab_4x4_v05_01_FPGAv1.bit WARPLab_4x4_v05_01_FPGAv1.bit][[BR]][http://warp.rice.edu/trac/export/1442/ResearchApps/PHY/WARPLAB/WARPLab_v05_1/ACE_Files/WARPLab_4x4_v05_01_FPGAv1.ace WARPLab_4x4_v05_01_FPGAv1.ace][[BR]] [http://warp.rice.edu/bigFiles/WARPLab_ReferenceDesign_4x4_v05_01_FPGAv1.zip WARPLab_ReferenceDesign_4x4_v05_01_FPGAv1.zip]  ||
    3941
    40 WARP v1 EDK Download: [http://warp.rice.edu/bigFiles/WARPLab_ReferenceDesign_2x2_v05_01_FPGAv1.zip 2 Radio],[http://warp.rice.edu/bigFiles/WARPLab_ReferenceDesign_4x4_v05_01_FPGAv1.zip 4 Radio]
    4142  * Builds upon the features of Version 5
    4243  * Support for both Version 1 and 2 of the FPGA Board