wiki:WARPLab

Version 29 (modified by chunter, 11 years ago) (diff)

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WARPLab 7

WARPLab is a framework for rapid physical layer prototyping that allows for coordination of arbitrary combinations of single and multi-antenna transmit and receive nodes. The extensible framework gives users the flexibility to develop and deploy large arrays of nodes to meet any application or research need.

The WARPLab reference design is an implementation of the WARPLab framework that allows many physical layer designs to be constructed and tested. The reference design combines MATLAB and FPGA implementations of the WARPLab framework modules that allow for easy extensibility and customization. While the reference design uses MATLAB to control nodes and perform signal processing, it also allows applications with strict latency requirements to move time critical processing in to the FPGA. The latest WARPLab 7 reference design runs on both WARP v2 and WARP v3 hardware. Users with WARP v1 hardware should use WARPLab 6.

WARPLab 7 is a complete rewrite of the original WARPLab framework. This rewrite was created and is maintained by engineers at Mango Communications.

What's New?

WARPLab 7 makes many significant improvements over previous WARPLab releases:

  • New object-oriented m-code framework
    • Segmented code for subsystems (baseband, RF interfaces, network I/O)
    • Built-in support for iterating over nodes and RF interfaces
    • Much cleaner scripts when dealing with multiple nodes and interfaces
    • Easy upgrades by separating some user extensions from core reference design
  • Packet "sniffing" logic (compatible with WARP v3 only)
    • Captures trigger packets in FPGA fabric
    • 10x reduction in node-to-node jitter in starting Tx/Rx cycles
    • Tx/Rx cycles start ~12usec sooner
  • Support for jumbo Ethernet frames up to 9014 bytes long, resulting in a significant performance increase (compatible with WARP v3 only)
  • Cross-platform (tested on Windows and Mac OSX)
  • Default buffers now 215 (32k) samples (800usec duration per Tx/Rx cycle) (compatible with WARP v3 only)
  • Built in latest Xilinx tools (ISE 14.4)
    • AXI bus architecture (compatible with WARP v3 only)

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