wiki:cores/fmc_bb_4da_bridge

FMC-BB-4DA Bridge (fmc_bb_4da_bridge)

The fmc_bb_4da_bridge core implements the output logic for interfacing user designs with the digital interfaces of the AD9116 DACs on the FMC-BB-4DA module. The AD9116 digital ports are double data rate (DDR) interfaces with interleaved I/Q. The fmc_bb_4da_bridge core uses ODDR primitives in the FPGA IOBs to efficiently translate between the external interleaved ports and internal separate busses. One fmc_bb_4da_bridge instance implements the digital interfaces for both AD9116 devices on the FMC-BB-4DA module.

The fmc_bb_4da_bridge core is packaged as a pcore to be instantiated in an XPS project. The design has been tested in hardware using Xilinx ISE 13.4. The fmc_bb_4da_bridge core does not attach to a processor bus, so there is no driver.

The latest revision of the core is v1.00.b, available in the repository: fmc_bb_4da_bridge_v1_00_b.

Internal Connections

The fmc_bb_4da_bridge core has inputs which must be connected to internal clock and data signals in the XPS project.

Clocks

There are two clock inputs which must be connected:

  • sys_samp_clk: must be synchronous with and valid for registering the user-supplied data signals
  • sys_samp_clk_90: must be a 90-degree phase-shifted version of sys_samp_clk (Virtex-6 MMCMs can generate this)

Data

There are four data ports, one per DAC output. The labels of these ports match the labels on the FMC-BB-4DA board ("DAC_A", "DAC_B", etc.).

  • user_DAC_A: data for DAC A
  • user_DAC_B: data for DAC B
  • user_DAC_C: data for DAC C
  • user_DAC_D: data for DAC D

The width of each port is configurable via an HDL parameter. These parameters are exposed via the "Customize IP Core" GUI in XPS. The width specified in the parameter must match the width of the signal tied to the corresponding port. The width must be <= 16 bits. Up to 12 MSB of the user-supplied signal will be used to drive the DAC's digital input. For user-supplied signals smaller than 12 bits, unused LSB will be driven to 0.

External Connections

The ports below must be mapped to top-level outputs in the XPS project, and constrained to the appropriate pins in the project UCF file.

Port Direction Width Connection
DAC_AB_DB Output 12 DACs A/B AD9116 data port
DAC_AB_CLK Output 1 DACs A/B AD9116 clock
DAC_AB_PINMD Output 1 DACs A/B AD9116 Pin Mode control (tied to 1)
DAC_AB_CLKMD Output 1 DACs A/B AD9116 Clock Mode control (tied to 0)
DAC_AB_FORMAT Output 1 DACs A/B AD9116 Format control (tied to 1)
DAC_AB_PWDN Output 1 DACs A/B AD9116 Power Down control (tied to 0)
DAC_CD_DB Output 12 DACs C/D AD9116 data port
DAC_CD_CLK Output 1 DACs C/D AD9116 clock
DAC_CD_PINMD Output 1 DACs C/D AD9116 Pin Mode control (tied to 1)
DAC_CD_CLKMD Output 1 DACs C/D AD9116 Clock Mode control (tied to 0)
DAC_CD_FORMAT Output 1 DACs C/D AD9116 Format control (tied to 1)
DAC_CD_PWDN Output 1 DACs C/D AD9116 Power Down control (tied to 0)

Instantiating the Core

The MHS and UCF snippets below show how to instantiate the fmc_bb_4da_bridge core in an XPS project for WARP v3.

In system.mhs:

#Top-level ports
...
##FMC-BB-4DA pins
# DAC data busses
 PORT DAC_AB_DB = DAC_AB_DB, DIR = O, VEC = [0:13]
 PORT DAC_CD_DB = DAC_CD_DB, DIR = O, VEC = [0:13]
# DAC_AB clock/control
 PORT DAC_AB_CLK = DAC_AB_CLK, DIR = O
 PORT DAC_AB_PINMD = DAC_AB_PINMD, DIR = O
 PORT DAC_AB_PWDN = DAC_AB_PWDN, DIR = O
 PORT DAC_AB_CLKMD = DAC_AB_CLKMD, DIR = O
 PORT DAC_AB_FORMAT = DAC_AB_FORMAT, DIR = O
# DAC_CD clock/control
 PORT DAC_CD_CLK = DAC_CD_CLK, DIR = O
 PORT DAC_CD_PINMD = DAC_CD_PINMD, DIR = O
 PORT DAC_CD_PWDN = DAC_CD_PWDN, DIR = O
 PORT DAC_CD_CLKMD = DAC_CD_CLKMD, DIR = O
 PORT DAC_CD_FORMAT = DAC_CD_FORMAT, DIR = O

...

BEGIN fmc_bb_4da_bridge
 PARAMETER INSTANCE = fmc_bb_4da_bridge_0
 PARAMETER HW_VER = 1.00.b
## Widths of user data ports
 PARAMETER USER_DAC_A_BITS = 12
 PARAMETER USER_DAC_B_BITS = 12
 PARAMETER USER_DAC_C_BITS = 12
 PARAMETER USER_DAC_D_BITS = 12
## Internal clocks
 PORT sys_samp_clk = clk_80MHz
 PORT sys_samp_clk_90 = clk_80MHz_90degphase
## User data ports
 PORT user_DAC_A = data_12_bits_for_DAC_A
 PORT user_DAC_B = data_12_bits_for_DAC_B
 PORT user_DAC_C = data_12_bits_for_DAC_C
 PORT user_DAC_D = data_12_bits_for_DAC_D
## Data outputs
 PORT DAC_AB_DB = DAC_AB_DB
 PORT DAC_CD_DB = DAC_CD_DB
## Clock outputs
 PORT DAC_AB_CLK = DAC_AB_CLK
 PORT DAC_CD_CLK = DAC_CD_CLK
## Control outputs
 PORT DAC_AB_PINMD = DAC_AB_PINMD
 PORT DAC_AB_PWDN = DAC_AB_PWDN
 PORT DAC_AB_CLKMD = DAC_AB_CLKMD
 PORT DAC_AB_FORMAT = DAC_AB_FORMAT
 PORT DAC_CD_PINMD = DAC_CD_PINMD
 PORT DAC_CD_PWDN = DAC_CD_PWDN
 PORT DAC_CD_CLKMD = DAC_CD_CLKMD
 PORT DAC_CD_FORMAT = DAC_CD_FORMAT
END

In system.ucf:

...

NET "DAC_AB_CLK" LOC = H20 | IOSTANDARD = LVCMOS25; #FMC_LA09_N
NET "DAC_AB_PINMD" LOC = F21 | IOSTANDARD = LVCMOS25; #FMC_LA00_CC_P
NET "DAC_AB_PWDN" LOC = B20 | IOSTANDARD = LVCMOS25; #FMC_LA01_CC_P
NET "DAC_AB_CLKMD" LOC = G20 | IOSTANDARD = LVCMOS25; #FMC_LA00_CC_N
NET "DAC_AB_FORMAT" LOC = E22 | IOSTANDARD = LVCMOS25; #FMC_LA02_P

NET "DAC_AB_DB<13>" LOC = F20 | IOSTANDARD = LVCMOS25; #FMC_LA07_N
NET "DAC_AB_DB<12>" LOC = A24 | IOSTANDARD = LVCMOS25; #FMC_LA08_N
NET "DAC_AB_DB<11>" LOC = F19 | IOSTANDARD = LVCMOS25; #FMC_LA07_P
NET "DAC_AB_DB<10>" LOC = E21 | IOSTANDARD = LVCMOS25; #FMC_LA05_N
NET "DAC_AB_DB<9>" LOC = A23 | IOSTANDARD = LVCMOS25; #FMC_LA08_P
NET "DAC_AB_DB<8>" LOC = G22 | IOSTANDARD = LVCMOS25; #FMC_LA06_N
NET "DAC_AB_DB<7>" LOC = D21 | IOSTANDARD = LVCMOS25; #FMC_LA05_P
NET "DAC_AB_DB<6>" LOC = D19 | IOSTANDARD = LVCMOS25; #FMC_LA04_N
NET "DAC_AB_DB<5>" LOC = G21 | IOSTANDARD = LVCMOS25; #FMC_LA06_P
NET "DAC_AB_DB<4>" LOC = E19 | IOSTANDARD = LVCMOS25; #FMC_LA04_P
NET "DAC_AB_DB<3>" LOC = C23 | IOSTANDARD = LVCMOS25; #FMC_LA03_N
NET "DAC_AB_DB<2>" LOC = B23 | IOSTANDARD = LVCMOS25; #FMC_LA03_P
NET "DAC_AB_DB<1>" LOC = C19 | IOSTANDARD = LVCMOS25; #FMC_LA01_CC_N
NET "DAC_AB_DB<0>" LOC = E23 | IOSTANDARD = LVCMOS25; #FMC_LA02_N

NET "DAC_CD_CLK" LOC = F13 | IOSTANDARD = LVCMOS25; #FMC_LA28_N
NET "DAC_CD_PINMD" LOC = D20 | IOSTANDARD = LVCMOS25; #FMC_LA11_N
NET "DAC_CD_PWDN" LOC = H13 | IOSTANDARD = LVCMOS25; #FMC_LA16_N
NET "DAC_CD_CLKMD" LOC = G12 | IOSTANDARD = LVCMOS25; #FMC_LA16_P
NET "DAC_CD_FORMAT" LOC = G13 | IOSTANDARD = LVCMOS25; #FMC_LA15_P

NET "DAC_CD_DB<13>" LOC = E13 | IOSTANDARD = LVCMOS25; #FMC_LA28_P
NET "DAC_CD_DB<12>" LOC = J10 | IOSTANDARD = LVCMOS25; #FMC_LA29_N
NET "DAC_CD_DB<11>" LOC = J11 | IOSTANDARD = LVCMOS25; #FMC_LA29_P
NET "DAC_CD_DB<10>" LOC = D11 | IOSTANDARD = LVCMOS25; #FMC_LA24_P
NET "DAC_CD_DB<9>" LOC = D12 | IOSTANDARD = LVCMOS25; #FMC_LA25_P
NET "DAC_CD_DB<8>" LOC = B13 | IOSTANDARD = LVCMOS25; #FMC_LA21_N
NET "DAC_CD_DB<7>" LOC = A11 | IOSTANDARD = LVCMOS25; #FMC_LA26_P
NET "DAC_CD_DB<6>" LOC = B12 | IOSTANDARD = LVCMOS25; #FMC_LA21_P
NET "DAC_CD_DB<5>" LOC = A14 | IOSTANDARD = LVCMOS25; #FMC_LA22_N
NET "DAC_CD_DB<4>" LOC = E14 | IOSTANDARD = LVCMOS25; #FMC_LA19_N
NET "DAC_CD_DB<3>" LOC = J12 | IOSTANDARD = LVCMOS25; #FMC_LA20_N
NET "DAC_CD_DB<2>" LOC = F14 | IOSTANDARD = LVCMOS25; #FMC_LA19_P
NET "DAC_CD_DB<1>" LOC = H12 | IOSTANDARD = LVCMOS25; #FMC_LA20_P
NET "DAC_CD_DB<0>" LOC = H14 | IOSTANDARD = LVCMOS25; #FMC_LA15_N

...

Source

The full hardware source code is available in the repository: PlatformSupport/CustomPeripherals/pcores/fmc_bb_4da_bridge_v1_00_b. The Verilog source code is made available under the WARP license.

Last modified 5 years ago Last modified on Feb 19, 2013, 11:13:55 AM