WARP v3 Radio Controller (radio_controller)
This core implements control interfaces for up to four MAX2829 transceivers, including both the digital control lines (TXEN, RXEN, etc.) and the MAX2829 SPI interface. The radio_controller driver provides user-callable functions to set the state and configure every parameter of the MAX2829.
The radio_controller core is packaged as a pcore which can instantiated in an XPS project. The design has been tested in hardware using Xilinx ISE 13.4.
Version note: This core is only compatible with WARP v3 hardware. The radio_controller 2.00.a core is available for WARP v2 which uses the (nearly) identical API as this core.
The radio_controller hardware manages both the digital control lines and the SPI interface of the MAX2829, as well as the power amplifier and RF switch. The sections below describe the functionality of the radio_controller hardware in detail.
The MAX2829 is always in one of five states: Transmit, Receive, Standby, Shutdown and Reset. The active state is set by the TXEN, RXEN and SHDN inputs. TXEN and RXEN are active high; SHDN is active low.
|Shutdown||0||0||0||All blocks except SPI interface are shutdown|
|Reset||0||1||1||All SPI registers returned to default values|
|Standby||1||0||0||Tx and Rx paths shutdown; PLL active if MIMO mode enabled|
|Transmit||1||1||0||2.4 or 5GHz Tx path active, depending on selected center frequency|
|Receive||1||0||1||2.4 or 5GHz Rx path active, depending on selected center frequency|
The MAX2829 implements a "MIMO mode", which keeps the PLL running in the Standby state. By keeping the PLL active the phase offset between multiple MAX2829s sharing a reference clock is held constant across Tx->Rx and Rx->Tx state transitions. MIMO mode is required to support PHY designs which use explicit calibration or feedback of phases between antennas (like beamforming). MIMO mode is not required to support PHY designs which explicitly train each spatial path with every transmission (like Alamouti STBC). The radio_controller driver enables MIMO mode by default.
The MAX2829 has an SPI interface for writing internal registers. Unfortunately this SPI interface is write-only. As a result the current state of the registers cannot be explicitly read and must be inferred by the controller based on all previous register writes since the last reset.
The radio_controller implements "mirror registers" which track the current state of the MAX2829 register bank. Whenever user code initiates an SPI write, the radio_controller HDL automatically updates the corresponding mirror register in the FPGA. This allows user code to read the current value of a MAX2829 register without having to explicitly track every register state in code.
The MAX2829 internal registers are reset to their default states only in the Reset state. The radio_controller HDL monitors the TXEN, RXEN and SHDN lines for a reset condition and reset the mirror registers whenever the corresponding MAX2829 is reset.
Refer to the driver documentation below for the functions which read and write the SPI and mirror registers.
RF Front End
The radio_controller logic also controls the state of the power amplifier and RF switch. The state of the PA and switch are automatically set by the radio_controller when the MAX2829 state changes. When the MAX2829 mode is Transmit, the radio_controller enables the correct PA (2.4 or 5GHz, depending on the programmed center frequency) and sets the RF switch to connect the PA output to the SMA jack. When the MAX2829 mode is Receive the radio_controller disables both PAs and connects the SMA jack to the MAX2829 Rx inputs.
When an RF interface is set to transmit mode, four things occur:
- MAX2829 state is set to Transmit (TXEN=1, RXEN=0, SHDN=1)
- Power amplifier is enabled (radio_controller selects correct PA based on MAX2829 center frequency)
- MAX2829 Tx gain is ramped from 0 to the user-specified target
- User logic begins supplying non-zero I/Q to DACs
The radio_controller HDL implements a simple state machine which controls the sequencing of these events. The state machine is started when user code calls radio_controller_TxEn(). The state machine asserts an output for each event following a programmed delay. The target Tx gain is also programmed by user code. Refer to the driver documentation below for the functions to control the Tx sequencing state machine and Tx gain ramp.
The radio_controller pcore includes a C driver to facilitate control of the MAX2829 from user code. Refer to the radio_controller driver documentation for more details.
All driver functions require the base memory address of the radio_controller pcore. This address is set in your XPS project. The EDK tools copy this address into a macro in the xparameters.h file when you generate a BSP. The auto-generated macro should be named XPAR_RADIO_CONTROLLER_0_BASEADDR (assuming your pcore instance is named radio_controller_0).
//Define our own macro, in case EDK changes its naming scheme in the future // Assumes pcore instance is named w3_ad_controller_0; confirm in xparameters.h #define RC_BASEADDR XPAR_RADIO_CONTROLLER_0_BASEADDR
The MAX2829 can tune to arbitrary frequencies in the 2.4 and 5GHz bands by setting values in the PLL configuration registers. Refer to the MAX2829 datasheet for the forumlas to calculate register settings for arbitrary center frequencies.
The radio_controller driver provides a function (radio_controller_setCenterFrequency()) to tune to the standard 802.11 center frequencies in both bands. The channel numbers and corresponding center frequencies are listed in the driver documentation.
The full hardware and software source code is available in the repository: PlatformSupport/CustomPeripherals/pcores/radio_controller_axi_v3_01_a. The VHDL, Verilog and C source code are made available under the WARP license.