Changes between Version 3 and Version 4 of cores/w3_ad_bridge


Ignore:
Timestamp:
Aug 12, 2012, 3:13:45 PM (12 years ago)
Author:
murphpo
Comment:

--

Legend:

Unmodified
Added
Removed
Modified

  • cores/w3_ad_bridge

    v3 v4  
    88
    99== Tx Path ==
    10 The w3_ad_bridge Tx path is illustrated below. The logic depicted here is replicated for each RF interface.
     10The w3_ad_bridge Tx path is illustrated below. The logic depicted here is replicated for each RF interface (RF A and RF B).
    1111
    1212[[Image(wiki:cores/w3_ad_bridge/files:w3_adBridge_Tx.png, nolink)]]
    … …  
    1616|| ad_RFA_TXD || Output || 12 || AD9963 TXD || RF A Tx data (DDR, I/Q interleaved) ||
    1717|| ad_RFA_TXCLK || Output || 1 || AD9963 TXCLK || RF A Tx data clock ||
    18 || ad_RFA_TXIQ || Output || 1 || AD9963 TXIQ || RF A Tx data select (not used) ||
     18|| ad_RFA_TXIQ || Output || 1 || AD9963 TXIQ || RF A Tx data select (ignored in DDR mode) ||
    1919|| ad_RFB_TXD || Output || 12 || AD9963 TXD || RF B Tx data (DDR, I/Q interleaved) ||
    2020|| ad_RFB_TXCLK || Output || 1 || AD9963 TXCLK || RF B Tx data clock ||
    21 || ad_RFB_TXIQ || Output || 1 || AD9963 TXIQ || RF B Tx data select  (not used) ||
     21|| ad_RFB_TXIQ || Output || 1 || AD9963 TXIQ || RF B Tx data select  (ignored in DDR mode) ||
    2222
    2323
    … …  
    2828|| user_RFA_TXD_I || Input || 12 || RF A Tx I samples from user design ||
    2929|| user_RFA_TXD_Q|| Input || 12 || RF A Tx Q samples from user design ||
    30 || user_RFA_TXIQ || Input || 1 || RF A Tx I/Q select (not used) ||
     30|| user_RFA_TXIQ || Input || 1 || RF A Tx I/Q select (ignored in DDR mode) ||
    3131|| user_RFB_TXD_I || Input || 12 || RF B Tx I samples from user design ||
    3232|| user_RFB_TXD_Q|| Input || 12 || RF B Tx Q samples from user design ||
    33 || user_RFB_TXIQ || Input || 1 || RF B Tx I/Q select (not used) ||
     33|| user_RFB_TXIQ || Input || 1 || RF B Tx I/Q select (ignored in DDR mode) ||
    3434
     35'''TXCLK''':
     36The AD9963 TXCLK input is used to capture the data presented on the TXD bus. In order to meet setup/hold requirements, the FPGA TXCLK output is a 90-degree phase shifted version of the clock signal for the TXD output. The TXCLK output is generated using the same IOB ODDR primitives as the TXD outputs. This design minimizes skew between the TXD and TXCLK signals.
     37
     38The user design must supply both sys_samp_clk_Tx and sys_samp_clk_Tx_90, assuring they are 90 degrees out of phase and synchronous to the input I/Q signals.
     39
     40'''TXIQ''':
     41The TXIQ ports are used by the AD9963 to de-interleave I/Q when the TXCLK runs at 2x the TXD data rate. The w3_ad_bridge implements a passthrough from user_RFx_TXIQ to ad_RFx_TXIQ.
     42
     43Our projects configure TXCLK to run at 1x the TXD data rate (i.e. DDR), so the TXIQ signal is not needed to de-interleave I/Q. The user_RFx_TXIQ ports are tied to GND in our reference projects.
     44
     45----
    3546
    3647== Rx Path ==