Changes between Version 5 and Version 6 of cores/w3_ad_bridge
- Timestamp:
- Aug 12, 2012, 3:23:10 PM (12 years ago)
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cores/w3_ad_bridge
v5 v6 6 6 7 7 The current version of the w3_ad_bridge core is [source:/PlatformSupport/CustomPeripherals/pcores/w3_ad_bridge_v3_00_g v3_00_g]. 8 9 Refer to the latest WARP v3 reference projects for the recommended instantiation of the w3_ad_bridge core. 8 10 9 11 == Tx Path == … … 33 35 || user_RFB_TXIQ || Input || 1 || RF B Tx I/Q select (ignored in DDR mode) || 34 36 35 === TXCLK === 37 '''TXCLK''' [[BR]] 36 38 The AD9963 TXCLK input is used to capture the data presented on the TXD bus. In order to meet setup/hold requirements, the FPGA TXCLK output is a 90-degree phase shifted version of the clock signal for the TXD output. The TXCLK output is generated using the same IOB ODDR primitives as the TXD outputs. This design minimizes skew between the TXD and TXCLK signals. 37 39 38 40 The user design must supply both sys_samp_clk_Tx and sys_samp_clk_Tx_90, assuring they are 90 degrees out of phase and synchronous to the input I/Q signals. 39 41 40 === TXIQ === 42 '''TXIQ''' [[BR]] 41 43 The TXIQ ports are used by the AD9963 to de-interleave I/Q when the TXCLK runs at 2x the TXD data rate. The w3_ad_bridge implements a passthrough from user_RFx_TXIQ to ad_RFx_TXIQ. 42 44 … … 49 51 [[Image(wiki:cores/w3_ad_bridge/files:w3_adBridge_Rx.png, nolink)]] 50 52 51 == Hardware == 53 '''External Ports:''' 54 ||= Port =||= Direction =||= Width =||= Connection =||= Description =|| 55 || ad_RFA_TRXD || Input || 12 || AD9963 TRXD || RF A Rx data (DDR, I/Q interleaved) || 56 || ad_RFA_TRXCLK || Input || 1 || AD9963 TRXCLK || RF A Rx data clock || 57 || ad_RFA_TRXIQ || Input || 1 || AD9963 TRXIQ || RF A Rx data select (ignored in DDR mode) || 58 || ad_RFB_TRXD || Input || 12 || AD9963 TRXD || RF B Rx data (DDR, I/Q interleaved) || 59 || ad_RFB_TRXCLK || Input || 1 || AD9963 TRXCLK || RF B Rx data clock || 60 || ad_RFB_TRXIQ || Input || 1 || AD9963 TRXIQ || RF B Rx data select (ignored in DDR mode) || 52 61 53 The MHS snippet below shows the w3_ad_bridge instantiation used in the WARP v3 reference projects. 62 '''Internal Ports:''' 63 ||= Port =||= Direction =||= Width =||= Description =|| 64 || sys_samp_clk_Rx || Input || 1 || Clock for user I/Q outputs || 65 || user_RFA_RXD_I || Output || 12 || RF A Rx I samples for user design || 66 || user_RFA_RXD_Q || Output || 12 || RF A Rx Q samples for user design || 67 || user_RFB_RXD_I || Output || 12 || RF B Rx I samples for user design || 68 || user_RFB_RXD_Q || Output || 12 || RF B Rx Q samples for user design || 54 69 55 {{{ 56 #!sh 57 58 #Top level ports 59 }}} 70 '''Clocks'''[[BR]] 71 The IDDR registers are clocked by the AD9963-generated TRXCLK. The IDDR outputs are re-registered through D flip flops clocked by the user-supplied sys_samp_clk_Rx. The user design must assure the AD9963 is configured to generate a TRXCLK at the same frequency as the user-supplied sys_samp_clk_Rx. 60 72 61 73 == Source == … … 63 75 The full hardware and software source code is available in the repository: [source:/PlatformSupport/CustomPeripherals/pcores/w3_ad_bridge_v3_00_g]. The VHDL, Verilog and C source code are made available under the [wiki:/license WARP license]. 64 76 65 66 77 == Changelog == 67 78 2012-Aug-12:
