Changes between Version 6 and Version 7 of cores/w3_ad_bridge

Timestamp:

Aug 12, 2012, 3:23:47 PM (12 years ago)

Author:

murphpo

Comment:

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cores/w3_ad_bridge

@@ -8 +8 @@
 
 Refer to the latest WARP v3 reference projects for the recommended instantiation of the w3_ad_bridge core.
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 == Tx Path ==
@@ -71 +73 @@
 The IDDR registers are clocked by the AD9963-generated TRXCLK. The IDDR outputs are re-registered through D flip flops clocked by the user-supplied sys_samp_clk_Rx. The user design must assure the AD9963 is configured to generate a TRXCLK at the same frequency as the user-supplied sys_samp_clk_Rx.
 
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 == Source ==
 
 The full hardware and software source code is available in the repository: [source:/PlatformSupport/CustomPeripherals/pcores/w3_ad_bridge_v3_00_g]. The VHDL, Verilog and C source code are made available under the [wiki:/license WARP license].
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 == Changelog ==