Changes between Version 10 and Version 11 of cores/w3_clock_controller

Timestamp:

Jan 29, 2015, 12:57:25 PM (9 years ago)

Author:

murphpo

Comment:

--

cores/w3_clock_controller

@@ -129 +129 @@
  * Set output to FPGA as LVDS, bypass divider
 }}}
+
+
+== Custom Configurations ==
+The default configurations described above are implemented in the program ROM of the PicoBlaze microcontroller in the w3_clock_controller_axi core. These defaults can be overridden by programing new register address/data values in the WARP v3 EEPROM. The PicoBlaze program checks the EEPROM for valid clock configuration values on boot. If valid configuration options are found the program loads these from the EEPROM, bypassing the defaults entirely.
+
+||= EEPROM Bytes =||= Byte Values =||= Description =||
+|| 15000:15001  || {{{[0xA5 0xCD]}}} || Magic delimiter value indicating valid clock config values in EEPROM ||
+||||||  '''RF Reference Clock Buffer Configs''' (up to 8 register values)  ||
+|| 15002:15017  || {{{[A0 D0 ... A7 D7]}}} || RF reference clock buffer config {{{NOCM}}} ||
+|| 15018:15033  || {{{[A0 D0 ... A7 D7]}}} || RF reference clock buffer config {{{CM_MMCX_A}}} ||
+|| 15034:15049  || {{{[A0 D0 ... A7 D7]}}} || RF reference clock buffer config {{{CM_MMCX_B}}} ||
+|| 15050:15065  || {{{[A0 D0 ... A7 D7]}}} || RF reference clock buffer config {{{CM_MMCX_C}}} ||
+|| 15066:15081  || {{{[A0 D0 ... A7 D7]}}} || RF reference clock buffer config {{{CM_PLL_A}}} ||
+|| 15082:15097  || {{{[A0 D0 ... A7 D7]}}} || RF reference clock buffer config {{{CM_PLL_B}}} ||
+|| 15098:15113  || {{{[A0 D0 ... A7 D7]}}} || RF reference clock buffer config {{{CM_PLL_C}}} ||
+||||||  '''Sampling Clock Buffer Configs''' (up to 8 register values)  ||
+|| 15130:15145  || {{{[A0 D0 ... A7 D7]}}} || Sampling clock buffer config {{{NOCM}}} ||
+|| 15146:15161  || {{{[A0 D0 ... A7 D7]}}} || Sampling clock buffer config {{{CM_MMCX_A}}} ||
+|| 15162:15177  || {{{[A0 D0 ... A7 D7]}}} || Sampling clock buffer config {{{CM_MMCX_B}}} ||
+|| 15178:15193  || {{{[A0 D0 ... A7 D7]}}} || Sampling clock buffer config {{{CM_MMCX_C}}} ||
+|| 15194:15209  || {{{[A0 D0 ... A7 D7]}}} || Sampling clock buffer config {{{CM_PLL_A}}} ||
+|| 15210:15225  || {{{[A0 D0 ... A7 D7]}}} || Sampling clock buffer config {{{CM_PLL_B}}} ||
+|| 15226:15241  || {{{[A0 D0 ... A7 D7]}}} || Sampling clock buffer config {{{CM_PLL_C}}} ||
+||||||  '''PLL Configs''' (up to 40 register values)  ||
+|| 15258:15337  || {{{[A0 D0 ... A39 D39]}}} || PLL config {{{NOCM}}} ||
+|| 15338:15417  || {{{[A0 D0 ... A39 D39]}}} || PLL config {{{CM_PLL_A}}} ||
+|| 15418:15497  || {{{[A0 D0 ... A39 D39]}}} || PLL config {{{CM_PLL_B}}} ||
+|| 15498:15577  || {{{[A0 D0 ... A39 D39]}}} || PLL config {{{CM_PLL_C}}} ||
+
+----
 
 [[Image(w3_clock_controller_block_diagram.png, width=500)]]