Changes between Version 12 and Version 13 of cores/w3_clock_controller


Ignore:
Timestamp:
Jan 29, 2015, 2:57:07 PM (9 years ago)
Author:
murphpo
Comment:

--

Legend:

Unmodified
Added
Removed
Modified

  • cores/w3_clock_controller

    v12 v13  
    4747}}}
    4848{{{#!td style="background: #fff"
    49 {{{NOCM}}}
     49{{{CFG_NOCM}}}
    5050}}}
    5151{{{#!td style="background: #fff"
    5252 * Select WARP v3 80MHz TCXO as sampling clock source
     53 * Set output to FPGA as LVDS, bypass divider
     54}}}
     55|----------------------------
     56{{{#!td rowspan=3 style="background: #fff"
     57CM-MMCX
     58}}}
     59{{{#!td style="background: #fff"
     60[[Image(cmmmcx_sipsw_cfgsel_10.png,nolink)]]
     61}}}
     62{{{#!td style="background: #fff"
     63{{{CFG_CMMMCX_A}}}
     64}}}
     65{{{#!td style="background: #fff"
     66 * Select WARP v3 80MHz TCXO as sampling clock source
     67 * Set output to FPGA as LVDS, bypass divider
     68}}}
     69|----------------------------
     70{{{#!td style="background: #fff"
     71[[Image(cmmmcx_sipsw_cfgsel_01.png,nolink)]]
     72}}}
     73{{{#!td style="background: #fff"
     74{{{CFG_CMMMCX_B}}}
     75}}}
     76{{{#!td style="background: #fff"
     77 * Select clock module (MMCX Jack "Samp In") as sampling clock source
     78 * Set output to FPGA as LVDS, bypass divider
     79}}}
     80|----------------------------
     81{{{#!td style="background: #fff"
     82[[Image(cmmmcx_sipsw_cfgsel_00.png,nolink)]]
     83}}}
     84{{{#!td style="background: #fff"
     85{{{CFG_CMMMCX_C}}}
     86}}}
     87{{{#!td style="background: #fff"
     88 * Select clock module (MMCX connector "Samp In") as sampling clock source
    5389 * Set output to FPGA as LVDS, bypass divider
    5490}}}
    … …  
    6197}}}
    6298{{{#!td style="background: #ffe"
    63 {{{CM_PLL_A}}}
     99{{{CFG_CMPLL_A}}}
    64100}}}
    65101{{{#!td style="background: #ffe"
    … …  
    74110}}}
    75111{{{#!td style="background: #ffe"
    76 {{{CM_PLL_B}}}
     112{{{CFG_CMPLL_B}}}
    77113}}}
    78114{{{#!td style="background: #ffe"
    … …  
    86122}}}
    87123{{{#!td style="background: #ffe"
    88 {{{CM_PLL_C}}}
     124{{{CFG_CMPLL_C}}}
    89125}}}
    90126{{{#!td style="background: #ffe"
    91127 * Set PLL reference clock frequency to 80MHz
    92128 * Select clock module (CM-PLL 80MHz VCXO) as sampling clock source
    93  * Set output to FPGA as LVDS, bypass divider
    94 }}}
    95 |----------------------------
    96 {{{#!td rowspan=3 style="background: #fff"
    97 CM-MMCX
    98 }}}
    99 {{{#!td style="background: #fff"
    100 [[Image(cmmmcx_sipsw_cfgsel_10.png,nolink)]]
    101 }}}
    102 {{{#!td style="background: #fff"
    103 {{{CM_MMCX_A}}}
    104 }}}
    105 {{{#!td style="background: #fff"
    106  * Select WARP v3 80MHz TCXO as sampling clock source
    107  * Set output to FPGA as LVDS, bypass divider
    108 }}}
    109 |----------------------------
    110 {{{#!td style="background: #fff"
    111 [[Image(cmmmcx_sipsw_cfgsel_01.png,nolink)]]
    112 }}}
    113 {{{#!td style="background: #fff"
    114 {{{CM_MMCX_B}}}
    115 }}}
    116 {{{#!td style="background: #fff"
    117  * Select clock module (MMCX Jack "Samp In") as sampling clock source
    118  * Set output to FPGA as LVDS, bypass divider
    119 }}}
    120 |----------------------------
    121 {{{#!td style="background: #fff"
    122 [[Image(cmmmcx_sipsw_cfgsel_00.png,nolink)]]
    123 }}}
    124 {{{#!td style="background: #fff"
    125 {{{CM_MMCX_C}}}
    126 }}}
    127 {{{#!td style="background: #fff"
    128  * Select clock module (MMCX connector "Samp In") as sampling clock source
    129129 * Set output to FPGA as LVDS, bypass divider
    130130}}}