Changes between Version 14 and Version 15 of cores/w3_clock_controller

Timestamp:

Jan 29, 2015, 4:43:23 PM (9 years ago)

Author:

murphpo

Comment:

--

cores/w3_clock_controller

@@ -40 +40 @@
 }}}
 |----------------------------
-{{{#!td style="background: #fff"
+{{{#!td style="background: #ffe"
 None
 }}}
-{{{#!td style="background: #fff"
+{{{#!td style="background: #ffe"
 ---
 }}}
-{{{#!td style="background: #fff"
+{{{#!td style="background: #ffe"
 {{{CFG_NOCM}}}
 }}}
-{{{#!td style="background: #fff"
+{{{#!td style="background: #ffe"
  * Select WARP v3 80MHz TCXO as sampling clock source
  * Set output to FPGA as LVDS, bypass divider
@@ -340 +340 @@
 == Source ==
 
-The full hardware and software source code is available in the repository: [source:/PlatformSupport/CustomPeripherals/pcores/w3_clock_controller_v3_01_b]. The VHDL, Verilog and C source code are made available under the [wiki:/license WARP license].
+The full hardware and software source code is available in the repository: [source:/PlatformSupport/CustomPeripherals/pcores/w3_clock_controller_axi_v4_00_a]. The VHDL, Verilog and C source code are made available under the [wiki:/license WARP license].