Changes between Version 15 and Version 16 of cores/w3_clock_controller

Timestamp:

Jan 29, 2015, 10:50:17 PM (9 years ago)

Author:

murphpo

Comment:

--

cores/w3_clock_controller

@@ -165 +165 @@
 
 ----
-
-[[Image(w3_clock_controller_block_diagram.png, width=500)]]
-
-
 
 [http://www.xilinx.com/products/intellectual-property/picoblaze.html#documentation Xilinx PicoBlaze documentation]
@@ -273 +269 @@
 }}}
 
-== Post-Configuration ==
-
-The WARP v3 board uses two AD9512 clock buffers:
- * Sampling clock buffer: distributes the sampling clock to the RF interfaces, FPGA, clock module header, and FMC slot
- * RF reference clock buffer: distributes the RF reference clock to the RF interfaces, clock module header, and FMC slot
-
-These buffers are configured via on-boar registers accessible via an SPI interface. The SPI pins for both buffers are tied to dedicated I/O pins on the v3 FPGA.
-
-The CM-PLL clock module uses one AD9511 PLL/buffer. When a CM-PLL module is mounted on the WARP v3 board the AD9511 SPI interface is also connected to dedicated FPGA pins.
-
-== Driver ==
-
-The w3_clock_controller pcore includes a C driver to facilitate control of the AD9512s from user code. Refer to the [//svn/WARP/PlatformSupport/CustomPeripherals/pcores/w3_clock_controller_v3_01_b/doc/html/api/index.html w3_clock_controller driver documentation] for more details.
-
-All driver functions require the base memory address of the w3_clock_controller pcore. This address is set in your XPS project. The EDK tools copy this address into a macro in the {{{xparameters.h}}} file when you generate a BSP. The auto-generated macro should be named {{{XPAR_W3_CLOCK_CONTROLLER_0_BASEADDR}}} (assuming your pcore instance is named {{{w3_CLOCK_controller_0}}}, as in our reference projects).
-
-{{{
-#!C
-//Define our own macro, in case EDK changes its naming scheme in the future
-// Assumes pcore instance is named w3_ad_controller_0; confirm in xparameters.h
-#define CLOCK_BASEADDR XPAR_W3_CLOCK_CONTROLLER_0_BASEADDR
-
-}}}
-
-== Sampling Clock Source ==
-
-Many user designs for WARP v3 use the sampling clock reference as the master clock for FPGA logic. Our [wiki:HardwareUsersGuides/WARPv3/TemplateProjects WARP v3 Template Projects] do this, for example. One implication of this approach is the sampling clock source must be stable before the FPGA logic attempts to use it. When the on-board clock is used, this is straightforward. When an off-board clock source is used (via a Clock Module) the FPGA logic must be held in reset until the sampling clock buffer can switch to the external cock source.
-
-The w3_clock_controller contains a small block to handle this "at boot" clock selection. Immediately after the FPGA is configured this block writes a handful of registers in the sampling clock buffer to configure the sampling clock input. The block asserts an "invalid" output to hold the rest of the FPGA design in reset until its register writes are complete. The "at boot" logic uses the 200MHz oscillator on WARP v3, which is always available (even when the rest of the FPGA design uses an off-board clock).
-
-The w3_clock_controller at boot logic uses the two switches on the CM-MMCX to select the clock mode. When both switches are down (logic 0) the off-board sampling clock will be selected. All other switch settings will use the on-board sampling clock. User software can interpret the other switch states as desired (i.e. to select on/off board RF reference clock, to en/disable CM-MMCX clock outputs, etc.).
-
-== Usage ==
-
-An important factor in configuring the WARP v3 clock buffers is whether the FPGA logic implementing the w3_clock_controller core is itself clocked by the sampling clock. If so, it is critical the properties of the AD9512->FPGA clock are not changed by user code at run-time. All other outputs from the AD9512 buffers can be changed as needed by user code.
-
-The w3_clock_controller driver provides functions to configure the AD9512 output dividers, thereby configuring the frequency of the clocks feeding the RF interface AD9963 chips (the ADC/DAC chips). It is critical that the AD9512->AD9963 clock frequency be consistent with all other rates in the FPGA->DAC and ADC->FPGA interfaces. The combination of AD9963 clock settings (DLL state, ADC/DAC clock source, etc.), AD9963 filter settings (interpolation/decimation rates), AD9512 dividers and internal FPGA->w3_ad_bridge clock connections must all agree. Refer to the [wiki:HardwareUsersGuides/WARPv3/RF WARP v3 User Guide RF section] for more details and examples of valid AD9512/AD9963/FPGA configurations.
-
-The MHS snippet below shows a typical use of the w3_clock_controller (taken from the [wiki:HardwareUsersGuides/WARPv3/TemplateProjects#OnBoardPeripheralsTemplateProject OnBoardPeriphs template project]).
-{{{#!sh
-BEGIN w3_clock_controller
- PARAMETER INSTANCE = w3_clock_controller_0
- PARAMETER HW_VER = 3.01.b
- PARAMETER C_BASEADDR = 0xc0400000
- PARAMETER C_HIGHADDR = 0xc040ffff
- BUS_INTERFACE SPLB = plb_primary
-#AD9512 SPI pins
- PORT rfref_spi_cs_n = clk_rfref_spi_cs_n
- PORT samp_spi_cs_n = clk_samp_spi_cs_n
- PORT samp_spi_mosi = clk_samp_spi_mosi
- PORT rfref_spi_mosi = clk_rfref_spi_mosi
- PORT samp_spi_sclk = clk_samp_spi_sclk
- PORT rfref_spi_sclk = clk_rfref_spi_sclk
- PORT samp_spi_miso = clk_samp_spi_miso
- PORT rfref_spi_miso = clk_rfref_spi_miso
-#At boot ports
- PORT at_boot_clk_in = clk_200MHz #always-running clock
- PORT at_boot_clk_in_valid = clk_gen_1_locked #valid indicator for at_boot_clk_in (when sourced from MMCM)
- PORT at_boot_config_sw = cm_mmcx_sw #CM-MMCX SIP switches
- PORT at_boot_clkbuf_clocks_invalid = mmcm_inputs_invalid #reset output
-#Software-readable input for user applications
- PORT usr_status = net_gnd
-END
-}}}
+== Driver Initialization ==
+
+The w3_clock_controller_axi core includes a C driver for use by applications running in a MicroBlaze processor. The MicroBlaze application must initialize the w3_clock_controller_axi driver by calling {{{clk_init()}}} early in the application {{{main()}}}.
+
+The {{{clk_init()}}} function applies the following settings:
+ * RF reference clock buffer
+  * Enables 40MHz reference clock to RF A and RF B transceivers (sets OUT3 as 40MHz CMOS, p/n outputs active)
+  * Disables output to FMC (OUT4)
+  * Disables unused outputs (OUT1, OUT2)
+ * Sampling clock buffer
+  * Enables 40MHz clock to ADC/DAC on RF A and RF B (enables OUT0/OUT2, sets divider to 2)
+  * Disables outputs to clock module (OUT1) and FMC (OUT4)
+
+== Software Application ==
+
+After calling {{{clk_init()}}} the software application should use the w3_clock_controller_axi driver to modify any application-specific clock settings. For example if an application uses the FMC-RF-2X245 module the RF reference and sampling clock outputs to the FMC slot must be enabled '''before''' the radio_controller attempts to initialize the RF transceivers  for RF C and RF D.
+
+The software application can also read the switches on clock modules to customize clock behavior at run time.
+
+Refer to the WARPLab Reference Design {{{node_clk_initialize()}}} function (in [browser:/ResearchApps/PHY/WARPLAB/WARPLab7/C_Code_Reference/wl_node.c?rev=4321#L545 wl_node.c]) for a good example of applying application-specific clock configurations.
+
+= Using the Core in XPS = 
+The w3_clock_controller_axi is packaged as a standard pcore, ready for instantiation in an XPS project. The core's AXI interface can be connected to an AXI lite or AXI interconnect. The must be assigned a memory address which is accessible by a MicroBlaze processor on the same interconnect.
+
+The w3_clock_controller_axi core ports are described in the table below. Some ports must be connected to top-level FPGA pins. Other ports must be connected to other cores in the XPS project. A typical system is illustrated in the block diagram below. Refer to the WARPLab Reference Design or 802.11 Reference Design for good examples of XPS projects integrating the w3_clock_controller_axi core.
+
+||= Port =||= Description =||
+|| S_AXI_ACLK  || Clock for core logic and AXI interface; should be synchronous with RF interface sampling clocks  ||
+|| S_AXI_*  || AXI slave interface ports; connect to AXI interconnect  ||
+|| at_boot_clk_in  || Clock for pre-boot configuration logic. Connect to a the WARP v3 200MHz oscillator.  ||
+|| at_boot_clk_in_valid  || Qualifier for at_boot_clk_in input. Set to 1 when at_boot_clk_in is stable.  ||
+|| at_boot_config_sw![2:0]  || 3-bit switch from clock module. Connect directly to IOBs. These pins must have {{{PULLUP}}} constraints.  ||
+|| at_boot_clkbuf_clocks_invalid  || Output indicating status of pre-boot configuration. Logic 0 indicates pre-boot configuration is complete.  Connect to MMCMs whose inputs use sampling or PLL clocks.  ||
+|| samp_spi_*  || SPI interface for sampling clock buffer. Connect directly to corresponding FPGA IOBs  ||
+|| samp_func      || Reset signal for sampling clock buffer. Connect directly to corresponding FPGA IOB ||
+|| rfref_spi_*  || SPI interface for RF reference clock buffer. Connect directly to corresponding FPGA IOBs  ||
+|| rfref_func     || Reset signal for RF reference clock buffer. Connect directly to corresponding FPGA IOB ||
+|| cm_spi_*  || SPI interface for CM-PLL clock module PLL/buffer. Connect directly to corresponding FPGA IOBs  ||
+|| cm_pll_status          || Status signal from the CM-PLL clock module PLL/buffer. Connect directly to corresponding FPGA IOB  ||
+|| pll_ref_clk  || Reference clock for the CM-PLL clock module PLL. Connect to the clock signal driven by the CM-PLL on pins 35/36 of the clock module header  ||
+
+[[Image(w3_clock_controller_block_diagram.png, width=500)]]
 
 == Source ==
 
 The full hardware and software source code is available in the repository: [source:/PlatformSupport/CustomPeripherals/pcores/w3_clock_controller_axi_v4_00_a]. The VHDL, Verilog and C source code are made available under the [wiki:/license WARP license].
+