Changes between Version 18 and Version 19 of cores/w3_clock_controller

Timestamp:

Jan 30, 2015, 10:53:56 AM (9 years ago)

Author:

murphpo

Comment:

--

cores/w3_clock_controller

@@ -129 +129 @@
  * Set output to FPGA as LVDS, bypass divider
 }}}
+
+The w3_clock_controller_axi core uses the Xilinx PicoBlaze microcontroller to execute the pre-boot clock configuration process. PicoBlaze is an 8-bit microcontroller implemented in the fabric of the FPGA. The PicoBlaze controller executes a program stored in a block RAM whose contents are initialized in the HDL. In effect this block RAM acts as a ROM for the PicoBlaze program. The program is written in assembly code and assembled using the PicoBlaze assembler provided free by Xilinx.
+
+For an overview of the PicoBlaze program, refer to [browser:/PlatformSupport/CustomPeripherals/pcores/w3_clock_controller_axi_v4_00_a/hdl/verilog/picoblaze_src/prog_clk_config_boot.psc prog_clk_config_boot.psc pseudo-code description]. The actual assembly program is available in [source:/PlatformSupport/CustomPeripherals/pcores/w3_clock_controller_axi_v4_00_a/hdl/verilog/picoblaze_src/prog_clk_config_boot.psm prog_clk_config_boot.psm].
+
+For more information about the PicoBlaze microcontroller:
+ * [http://www.xilinx.com/products/intellectual-property/picoblaze.html#documentation Xilinx PicoBlaze documentation]
+ * [http://www.xilinx.com/ipcenter/processor_central/picoblaze/member/ Xilinx PicoBlaze source and tools] - w3_clock_controller_axi HDL uses PicoBlaze version 6 (KCPSM6) Rev 9
 
 
@@ -166 +174 @@
 ----
 
-[http://www.xilinx.com/products/intellectual-property/picoblaze.html#documentation Xilinx PicoBlaze documentation]
-
-[http://www.xilinx.com/ipcenter/processor_central/picoblaze/member/ Xilinx PicoBlaze source and tools] - w3_clock_controller_axi HDL uses PicoBlaze version 6 (KCPSM6) Rev 9
-
-PicoBlaze pseudo code - see [source:/PlatformSupport/CustomPeripherals/pcores/w3_clock_controller_axi_v4_00_a/hdl/verilog/picoblaze_src/prog_clk_config_boot.psm prog_clk_config_boot.psm] for actual assembly code:
-{{{
-#!c
-
-main() {
-
-        if(no_clock_module_mounted) {
-                load_configuration(DEV_RF_REF, CFG_NOCM)
-                load_configuration(DEV_SAMP, CFG_NOCM)
-                load_configuration(DEV_PLL, CFG_NOCM)
-                config_complete()
-        }
-
-        if(cm_mmcx_mounted) {
-          sw = read_cm_mmcx_sip_sw() //Read SIP switch
-  
-                if(sw == off_off) {
-                        //Up-Up switches -> ignore clock module
-                        load_configuration(DEV_RF_REF, CFG_NOCM)
-                        load_configuration(DEV_SAMP, CFG_NOCM)
-                        load_configuration(DEV_PLL, CFG_NOCM)
-                } else if(sw == off_on) {
-                        //Up-Down switches -> Config A
-                        load_configuration(DEV_RF_REF, CFG_CMMMCX_A)
-                        load_configuration(DEV_SAMP, CFG_CMMMCX_A)
-                } else if(sw == on_off) {
-                        //Down-Up switches -> Config B
-                        load_configuration(DEV_RF_REF, CFG_CMMMCX_B)
-                        load_configuration(DEV_SAMP, CFG_CMMMCX_B)
-                } else if(sw == on_on) {
-                        //Down-Up switches -> Config C
-                        load_configuration(DEV_RF_REF, CFG_CMMMCX_C)
-                        load_configuration(DEV_SAMP, CFG_CMMMCX_C)
-                }
-  
-          config_complete()
-        }
-
-        if(cm_pll_mounted) {
-                sw = read_cm_pll_dip_sw() //Read 2 LSB of DIP switch
-
-                if(sw == off_off) {
-                        //Down-Down switches -> ignore clock module
-                        load_configuration(DEV_RF_REF, CFG_NOCM)
-                        load_configuration(DEV_SAMP, CFG_NOCM)
-                        load_configuration(DEV_PLL, CFG_NOCM)
-                        config_complete()
-                }
-        
-                wait_for_pll_refclk()
-        
-                if(sw == off_on) {
-                        //Down-Up switches -> Config A
-                        load_configuration(DEV_RF_REF, CFG_CMPLL_A)
-                        load_configuration(DEV_SAMP, CFG_CMPLL_A)
-                        load_configuration(DEV_PLL, CFG_CMPLL_A)
-                } else if(sw == on_off) {
-                        //Up-Down switches -> Config B
-                        load_configuration(DEV_RF_REF, CFG_CMPLL_B)
-                        load_configuration(DEV_SAMP, CFG_CMPLL_B)
-                        load_configuration(DEV_PLL, CFG_CMPLL_B)
-                } else if(sw == on_on) {
-                        //Up-Up switches -> Config C
-                        load_configuration(DEV_RF_REF, CFG_CMPLL_C)
-                        load_configuration(DEV_SAMP, CFG_CMPLL_C)
-                        load_configuration(DEV_PLL, CFG_CMPLL_C)
-                }
-
-                wait_for_pll_lock()
-
-                config_complete()
-        }
-}
-
-load_configuration(req_device, req_cfg) {
-        if(eeprom[15000] == 0xA5 && eeprom[15001] == 0xCD) {
-                cfg_data = copy_cfg_from_eeprom(req_device, req_cfg)
-        } else {
-                cfg_data = copy_cfg_from_rom(req_device, req_cfg)
-        }
-
-        write_cfg_to_device(req_device, cfg_data)
-}
-
-wait_for_pll_refclk() {
-        while(read_pll_refclk_status != TOGGLING) {}
-}
-
-wait_for_pll_lock() {
-        while(read_pll_lock_status != LOCKED) {}
-}
-
-config_complete() {
-  clear_mmcm_reset() //Starts clocks to FPGA, allows MicroBlaze subsystem to boot
-  halt()
-}
-
-}}}
-
 == Driver Initialization ==