Changes between Version 19 and Version 20 of cores/w3_clock_controller

Timestamp:

Jan 30, 2015, 10:55:57 AM (9 years ago)

Author:

murphpo

Comment:

--

cores/w3_clock_controller

@@ -132 +132 @@
 The w3_clock_controller_axi core uses the Xilinx PicoBlaze microcontroller to execute the pre-boot clock configuration process. PicoBlaze is an 8-bit microcontroller implemented in the fabric of the FPGA. The PicoBlaze controller executes a program stored in a block RAM whose contents are initialized in the HDL. In effect this block RAM acts as a ROM for the PicoBlaze program. The program is written in assembly code and assembled using the PicoBlaze assembler provided free by Xilinx.
 
-For an overview of the PicoBlaze program, refer to [browser:/PlatformSupport/CustomPeripherals/pcores/w3_clock_controller_axi_v4_00_a/hdl/verilog/picoblaze_src/prog_clk_config_boot.psc prog_clk_config_boot.psc pseudo-code description]. The actual assembly program is available in [source:/PlatformSupport/CustomPeripherals/pcores/w3_clock_controller_axi_v4_00_a/hdl/verilog/picoblaze_src/prog_clk_config_boot.psm prog_clk_config_boot.psm].
+For an overview of the PicoBlaze program, refer to [browser:/PlatformSupport/CustomPeripherals/pcores/w3_clock_controller_axi_v4_00_a/hdl/verilog/picoblaze_src/prog_clk_config_boot.psc prog_clk_config_boot.psc] pseudo-code. The actual assembly program is available in [source:/PlatformSupport/CustomPeripherals/pcores/w3_clock_controller_axi_v4_00_a/hdl/verilog/picoblaze_src/prog_clk_config_boot.psm prog_clk_config_boot.psm].
+
+It is '''not''' necessary to modify the PicoBlaze program to customize the register values written by the pre-boot logic. The PicoBlaze program can read custom configurations from the WARP v3 EEPROM, requiring no changes to the HDL or pre-built reference design hardware projects. Refer to the Custom Configurations section below for more details.
 
 For more information about the PicoBlaze microcontroller: