Changes between Version 20 and Version 21 of cores/w3_clock_controller
- Timestamp:
- Feb 6, 2015, 11:32:04 AM (9 years ago)
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cores/w3_clock_controller
v20 v21 58 58 }}} 59 59 {{{#!td style="background: #fff" 60 [[Image(cmmmcx_sipsw_cfgsel_01.png,nolink)]] 61 }}} 62 {{{#!td style="background: #fff" 63 {{{CFG_CMMMCX_A}}} 64 }}} 65 {{{#!td style="background: #fff" 66 * Select WARP v3 80MHz TCXO as sampling clock source 67 * Set output to FPGA as LVDS, bypass divider 68 }}} 69 |---------------------------- 70 {{{#!td style="background: #fff" 60 71 [[Image(cmmmcx_sipsw_cfgsel_10.png,nolink)]] 61 }}}62 {{{#!td style="background: #fff"63 {{{CFG_CMMMCX_A}}}64 }}}65 {{{#!td style="background: #fff"66 * Select WARP v3 80MHz TCXO as sampling clock source67 * Set output to FPGA as LVDS, bypass divider68 }}}69 |----------------------------70 {{{#!td style="background: #fff"71 [[Image(cmmmcx_sipsw_cfgsel_01.png,nolink)]]72 72 }}} 73 73 {{{#!td style="background: #fff"
