Changes between Version 21 and Version 22 of cores/w3_clock_controller


Ignore:
Timestamp:
Jun 29, 2015, 9:12:42 AM (5 years ago)
Author:
chunter
Comment:

--

Legend:

Unmodified
Added
Removed
Modified
  • cores/w3_clock_controller

    v21 v22  
    2222 1. Selecting (and possibly configuring) the clock source for the sampling clock buffer
    2323
    24 These steps require writing registers in the AD9512 buffer via its SPI interface. However the primary SPI master in the w3_clock_controller_axi core is part of logic attached to the AXI interconnected, clocked by the (not yet running) master clock. Thus the w3_clock_controller_axi HDL integrates a secondary SPI controller to perform initial setup of the clock circuits.
     24These steps require writing registers in the AD9512 buffer via its SPI interface. However the primary SPI master in the w3_clock_controller_axi core is part of logic attached to the AXI interconnect, clocked by the (not yet running) master clock. Thus the w3_clock_controller_axi HDL integrates a secondary SPI controller to perform initial setup of the clock circuits.
    2525
    2626The w3_clock_controller_axi HDL also supports run-time selection of various clock configurations using the switches on the CM-PLL and CM-MMCX clock modules. The core implements 7 configurations by default: