Changes between Version 3 and Version 4 of cores/w3_clock_controller

Timestamp:

Jan 28, 2015, 4:13:31 PM (9 years ago)

Author:

murphpo

Comment:

--

cores/w3_clock_controller

@@ -1 @@
- = WARP v3 Clock Controller (w3_clock_controller) =
+ = WARP v3 Clock Controller (w3_clock_controller_axi) =
 
 This core implements an SPI master for reading/writing registers in the AD9512 clock buffers on the WARP v3 board. For details about how these buffers are connected to the FPGA and RF interfaces, refer to the [wiki:HardwareUsersGuides/WARPv3/Clocking WARP v3 User Guide Clocking] section.
 
-The w3_clock_controller core is packaged as a pcore which can instantiated in an XPS project. The design has been tested in hardware using Xilinx ISE 13.4.
+This core also manages the interfaces on the CM-MMCX and CM-PLL clock modules for WARP v3.
+
+The w3_clock_controller_axi core is packaged as a pcore which can instantiated in an XPS project. The design has been tested in hardware using Xilinx ISE 14.4.
 
 == Hardware ==
 
-The WARP v3 board uses two AD9512 clock buffers: one for distributing the sampling clock (to the RF interfaces, FPGA and FMC slot) and one for distributing the RF reference clock (to the RF interfaces and FMC slot). The w3_clock_controller HDL implements parallel SPI interfaces, one per AD9512 buffer. There are 4 SPI pins per buffer which must be connected to the corresponding FPGA pins. Refer to the WARP v3 reference projects for examples of known-good hardware configurations.
+The WARP v3 board uses two AD9512 clock buffers:
+ * Sampling clock buffer: distributes the sampling clock to the RF interfaces, FPGA, clock module header, and FMC slot
+ * RF reference clock buffer: distributes the RF reference clock to the RF interfaces, clock module header, and FMC slot.
+
+These buffers are configured via on-boar registers accessible via an SPI interface. The SPI pins for both buffers are tied to dedicated I/O pins on the v3 FPGA.
+
+The CM-PLL clock module uses one AD9511 PLL/buffer. When a CM-PLL module is mounted on the WARP v3 board the AD9511 SPI interface is also connected to dedicated FPGA pins.
+
+
 
 == Driver ==