Changes between Version 4 and Version 5 of cores/w3_clock_controller

Timestamp:

Jan 28, 2015, 9:41:03 PM (9 years ago)

Author:

murphpo

Comment:

--

cores/w3_clock_controller

@@ -1 +1 @@
  = WARP v3 Clock Controller (w3_clock_controller_axi) =
 
-This core implements an SPI master for reading/writing registers in the AD9512 clock buffers on the WARP v3 board. For details about how these buffers are connected to the FPGA and RF interfaces, refer to the [wiki:HardwareUsersGuides/WARPv3/Clocking WARP v3 User Guide Clocking] section.
-
-This core also manages the interfaces on the CM-MMCX and CM-PLL clock modules for WARP v3.
+This core implements an SPI master for reading/writing registers in the AD9512 clock buffers on the WARP v3 board. For details about how these buffers are connected to the FPGA and RF interfaces, refer to the [wiki:HardwareUsersGuides/WARPv3/Clocking WARP v3 User Guide Clocking] section. This core also manages the interfaces on the CM-MMCX and CM-PLL clock modules for WARP v3.
 
 The w3_clock_controller_axi core is packaged as a pcore which can instantiated in an XPS project. The design has been tested in hardware using Xilinx ISE 14.4.
 
-== Hardware ==
+== Overview ==
+
+Clock configuration in a WARP v3 FPGA design occurs in three stages:
+ 1) '''Pre-boot:''' the minimum set of registers are written directly by the w3_clock_controller_axi HDL to achieve an 80MHz clock from the sampling clock buffer to the FPGA. All FPGA logic clocked by the sampling clock
+ 2) '''Driver initialization:''' the w3_clock_controller_axi driver {{{clk_init()}}} function writes additional registers in the sampling and RF reference clock buffers, establishing a default configuration suitable for most applications
+ 3) '''Software application:''' the user application running in the MicroBlaze calls other functions in the w3_clock_controller_axi driver to customize the clock configuration
+
+The sections below describe these three stages in detail.
+
+=== Pre-Boot Configuration ===
+
+In a typical FPGA design for WARP v3 most of the FPGA logic is clocked synchronous to the digital I/Q signals for the RF interfaces. This is true for both the [wiki:802.11 802.11 Reference Design] and [wiki:WARPLab WARPLab Reference Design], which use an 80MHz master clock sourced from the sampling clock buffer. In these designs the sampling clock signal is fed into clock management circuits in the FPGA (IBUFG, MMCM, etc) and is distributed across the chip. These circuits must be held in reset until a valid sampling clock is present at the FPGA input pins.
+
+PicoBlaze pseudo code:
+{{{#!C
+main() {
+
+        if(no_clock_module_mounted) {
+          load_configuration(CFG_NOCM)
+          config_complete()
+        }
+
+        if(cm_mmcx_mounted) {
+          sw = read_cm_mmcx_sip_sw() //Read SIP switch
+  
+                if(sw == off_off) {
+                        //Up-Up switches -> ignore clock module
+                        load_configuration(CFG_NOCM)
+                } else if(sw == off_on) {
+                        //Up-Down switches -> Config A
+                        load_configuration(CFG_CMMMCX_A)
+                } else if(sw == on_off) {
+                        //Down-Up switches -> Config B
+                        load_configuration(CFG_CMMMCX_B)
+                } else if(sw == on_on) {
+                        //Down-Up switches -> Config C
+                        load_configuration(CFG_CMMMCX_C)
+                }
+  
+          config_complete()
+        }
+
+        if(cm_pll_mounted) {
+                sw = read_cm_pll_dip_sw() //Read 2 LSB of DIP switch
+
+                if(sw == off_off) {
+                        //Down-Down switches -> ignore clock module
+                        load_configuration(CFG_NOCM)
+                        config_complete()
+                }
+        
+                wait_for_pll_refclk()
+        
+                if(sw == off_on) {
+                        //Down-Up switches -> Config A
+                        load_configuration(CFG_CMPLL_A)
+                } else if(sw == on_off) {
+                        //Up-Down switches -> Config B
+                        load_configuration(CFG_CMPLL_B)
+                } else if(sw == on_on) {
+                        //Up-Up switches -> Config C
+                        load_configuration(CFG_CMPLL_C)
+                }
+
+                wait_for_pll_lock()
+
+                config_complete()
+        }
+}
+
+wait_for_pll_refclk() {
+        while(read_pll_refclk_status != TOGGLING) {}
+}
+
+wait_for_pll_lock() {
+        while(read_pll_lock_status != LOCKED) {}
+}
+
+config_complete() {
+  clear_mmcm_reset() //Starts clocks to FPGA, allows MicroBlaze subsystem to boot
+  halt()
+}
+
+}}}
+
+== Post-Configuration ==
 
 The WARP v3 board uses two AD9512 clock buffers:
  * Sampling clock buffer: distributes the sampling clock to the RF interfaces, FPGA, clock module header, and FMC slot
- * RF reference clock buffer: distributes the RF reference clock to the RF interfaces, clock module header, and FMC slot.
+ * RF reference clock buffer: distributes the RF reference clock to the RF interfaces, clock module header, and FMC slot
 
 These buffers are configured via on-boar registers accessible via an SPI interface. The SPI pins for both buffers are tied to dedicated I/O pins on the v3 FPGA.
 
 The CM-PLL clock module uses one AD9511 PLL/buffer. When a CM-PLL module is mounted on the WARP v3 board the AD9511 SPI interface is also connected to dedicated FPGA pins.
-
-
 
 == Driver ==