Changes between Version 5 and Version 6 of cores/w3_clock_controller

Timestamp:

Jan 28, 2015, 10:32:04 PM (9 years ago)

Author:

murphpo

Comment:

--

cores/w3_clock_controller

@@ -16 +16 @@
 === Pre-Boot Configuration ===
 
-In a typical FPGA design for WARP v3 most of the FPGA logic is clocked synchronous to the digital I/Q signals for the RF interfaces. This is true for both the [wiki:802.11 802.11 Reference Design] and [wiki:WARPLab WARPLab Reference Design], which use an 80MHz master clock sourced from the sampling clock buffer. In these designs the sampling clock signal is fed into clock management circuits in the FPGA (IBUFG, MMCM, etc) and is distributed across the chip. These circuits must be held in reset until a valid sampling clock is present at the FPGA input pins.
+In a typical FPGA design for WARP v3 most of the FPGA logic is clocked synchronous to the RF interface digital I/Q signals. This is true for both the [wiki:802.11 802.11 Reference Design] and [wiki:WARPLab WARPLab Reference Design], which use an 80MHz master clock sourced from the sampling clock buffer. In these designs the sampling clock signal is fed into clock management circuits in the FPGA (IBUFG, MMCM, etc) and is distributed across the chip. These circuits must be held in reset until a valid sampling clock is present at the FPGA input pins.
+
+Establishing a stable 80MHz clock from the sampling clock buffer requires:
+ 1) Selecting (and possibly configuring) the clock source for the sampling clock buffer
+ 2) Configuring the divider and logic level of the buffer's output to the FPGA
+
+These steps require writing registers in the AD9512 buffer via its SPI interface. However the primary SPI master in the w3_clock_controller_axi core is part of logic attached to the AXI interconnected, clocked by the (not yet running) master clock. Thus the w3_clock_controller_axi HDL integrates a secondary SPI controller to perform initial setup of the clock circuits.
+
 
 PicoBlaze pseudo code: