Changes between Version 6 and Version 7 of cores/w3_clock_controller

Timestamp:

Jan 28, 2015, 10:57:15 PM (9 years ago)

Author:

murphpo

Comment:

--

cores/w3_clock_controller

@@ -24 +24 @@
 These steps require writing registers in the AD9512 buffer via its SPI interface. However the primary SPI master in the w3_clock_controller_axi core is part of logic attached to the AXI interconnected, clocked by the (not yet running) master clock. Thus the w3_clock_controller_axi HDL integrates a secondary SPI controller to perform initial setup of the clock circuits.
 
+[[Image(w3_clock_controller_block_diagram.png, width=500)]]
 
-PicoBlaze pseudo code:
+
+
+[http://www.xilinx.com/products/intellectual-property/picoblaze.html#documentation Xilinx PicoBlaze documentation]
+
+[http://www.xilinx.com/ipcenter/processor_central/picoblaze/member/ Xilinx PicoBlaze source and tools] - w3_clock_controller_axi HDL uses PicoBlaze version 6 (KCPSM6) Rev 9
+
+PicoBlaze pseudo code - see [source:/PlatformSupport/CustomPeripherals/pcores/w3_clock_controller_axi_v4_00_a/hdl/verilog/picoblaze_src/prog_clk_config_boot.psm prog_clk_config_boot.psm] for actual assembly code:
 {{{#!C
 main() {