Changes between Version 7 and Version 8 of cores/w3_clock_controller

Timestamp:

Jan 28, 2015, 11:40:50 PM (9 years ago)

Author:

murphpo

Comment:

--

cores/w3_clock_controller

@@ -8 +8 @@
 
 Clock configuration in a WARP v3 FPGA design occurs in three stages:
- 1) '''Pre-boot:''' the minimum set of registers are written directly by the w3_clock_controller_axi HDL to achieve an 80MHz clock from the sampling clock buffer to the FPGA. All FPGA logic clocked by the sampling clock
- 2) '''Driver initialization:''' the w3_clock_controller_axi driver {{{clk_init()}}} function writes additional registers in the sampling and RF reference clock buffers, establishing a default configuration suitable for most applications
- 3) '''Software application:''' the user application running in the MicroBlaze calls other functions in the w3_clock_controller_axi driver to customize the clock configuration
+ 1. '''Pre-boot:''' the minimum set of registers are written directly by the w3_clock_controller_axi HDL to achieve an 80MHz clock from the sampling clock buffer to the FPGA. All FPGA logic clocked by the sampling clock
+ 1. '''Driver initialization:''' the w3_clock_controller_axi driver {{{clk_init()}}} function writes additional registers in the sampling and RF reference clock buffers, establishing a default configuration suitable for most applications
+ 1. '''Software application:''' the user application running in the MicroBlaze calls other functions in the w3_clock_controller_axi driver to customize the clock configuration
 
 The sections below describe these three stages in detail.
@@ -19 +19 @@
 
 Establishing a stable 80MHz clock from the sampling clock buffer requires:
- 1) Selecting (and possibly configuring) the clock source for the sampling clock buffer
- 2) Configuring the divider and logic level of the buffer's output to the FPGA
+ 1. Configuring the divider and logic level of the buffer's output to the FPGA
+ 1. Selecting (and possibly configuring) the clock source for the sampling clock buffer
 
 These steps require writing registers in the AD9512 buffer via its SPI interface. However the primary SPI master in the w3_clock_controller_axi core is part of logic attached to the AXI interconnected, clocked by the (not yet running) master clock. Thus the w3_clock_controller_axi HDL integrates a secondary SPI controller to perform initial setup of the clock circuits.
+
+The w3_clock_controller_axi HDL also supports run-time selection of various clock configurations using the switches on the CM-PLL and CM-MMCX clock modules. The core implements 7 configurations by default:
+
+
+{{{#!th
+Clock Module
+}}}
+{{{#!th
+Switches
+}}}
+{{{#!th
+Config
+}}}
+{{{#!th
+Default Settings
+}}}
+|----------------------------
+{{{#!td style="background: #fff"
+None
+}}}
+{{{#!td style="background: #fff"
+---
+}}}
+{{{#!td style="background: #fff"
+---
+}}}
+{{{#!td style="background: #fff"
+ * Select WARP v3 80MHz TCXO as sampling clock source
+ * Set output to FPGA as LVDS, bypass divider
+}}}
+|----------------------------
+{{{#!td rowspan=3 style="background: #ffe"
+CM-PLL
+}}}
+{{{#!td style="background: #ffe"
+[[Image(cmpll_dipsw_cfgsel_101.png,nolink)]]
+}}}
+{{{#!td style="background: #ffe"
+CM_PLL_A
+}}}
+{{{#!td style="background: #ffe"
+ * Configure RF reference clock buffer to output 10MHz to clock module
+ * Set PLL reference clock frequency to 10MHz
+ * Select clock module (CM-PLL 80MHz VCXO) as sampling clock source
+ * Set output to FPGA as LVDS, bypass divider
+}}}
+|----------------------------
+{{{#!td style="background: #ffe"
+[[Image(cmpll_dipsw_cfgsel_110.png,nolink)]]
+}}}
+{{{#!td style="background: #ffe"
+CM_PLL_B
+}}}
+{{{#!td style="background: #ffe"
+ * Set PLL reference clock frequency to 10MHz
+ * Select clock module (CM-PLL 80MHz VCXO) as sampling clock source
+ * Set output to FPGA as LVDS, bypass divider
+}}}
+|----------------------------
+{{{#!td style="background: #ffe"
+[[Image(cmpll_dipsw_cfgsel_111.png,nolink)]]
+}}}
+{{{#!td style="background: #ffe"
+CM_PLL_C
+}}}
+{{{#!td style="background: #ffe"
+ * Set PLL reference clock frequency to 80MHz
+ * Select clock module (CM-PLL 80MHz VCXO) as sampling clock source
+ * Set output to FPGA as LVDS, bypass divider
+}}}
+|----------------------------
+{{{#!td rowspan=3 style="background: #fff"
+CM-MMCX
+}}}
+{{{#!td style="background: #fff"
+[[Image(cmmmcx_sipsw_cfgsel_10.png,nolink)]]
+}}}
+{{{#!td style="background: #fff"
+CM_MMCX_A
+}}}
+{{{#!td style="background: #fff"
+ * Select WARP v3 80MHz TCXO as sampling clock source
+ * Set output to FPGA as LVDS, bypass divider
+}}}
+|----------------------------
+{{{#!td style="background: #fff"
+[[Image(cmmmcx_sipsw_cfgsel_01.png,nolink)]]
+}}}
+{{{#!td style="background: #fff"
+CM_MMCX_B
+}}}
+{{{#!td style="background: #fff"
+ * Select clock module (MMCX Jack "Samp In") as sampling clock source
+ * Set output to FPGA as LVDS, bypass divider
+}}}
+|----------------------------
+{{{#!td style="background: #fff"
+[[Image(cmmmcx_sipsw_cfgsel_00.png,nolink)]]
+}}}
+{{{#!td style="background: #fff"
+CM_MMCX_C
+}}}
+{{{#!td style="background: #fff"
+ * Select clock module (MMCX Jack "Samp In") as sampling clock source
+ * Set output to FPGA as LVDS, bypass divider
+}}}
 
 [[Image(w3_clock_controller_block_diagram.png, width=500)]]