WARP v3 IIC EEPROM Master (w3_iic_eeprom)

This core implements an IIC master for accessing the IIC EEPROM on the WARP v3 board. The core provides a PLBv46 slave interface for control from user code.

The w3_iic_eeprom core is packaged as a pcore which can instantiated in an XPS project. The design has been tested in hardware using Xilinx ISE 13.4.


The MHS snippet below shows the w3_iic_eeprom instantiation used in the WARP v3 reference projects. The memory address is intentionally invalid; you must run "Generate Addresses" after adding the core.

Note that the top-level port name and internal net names are identical. This is a requirement imposed by XPS for connecting the tri-state IIC signals.

#Top level ports
 PORT IIC_EEPROM_iic_scl_pin = IIC_EEPROM_iic_scl_pin, DIR = IO
 PORT IIC_EEPROM_iic_sda_pin = IIC_EEPROM_iic_sda_pin, DIR = IO
BEGIN w3_iic_eeprom
 PARAMETER INSTANCE = w3_iic_eeprom_0
 BUS_INTERFACE SPLB = plb_primary
 PORT iic_scl = IIC_EEPROM_iic_scl_pin
 PORT iic_sda = IIC_EEPROM_iic_sda_pin


The w3_iic_eeprom pcore includes a C driver to facilitate accessing the EEPROM from user code. A simple example of using the driver is given below. Refer to the w3_iic_eeprom driver documentation for more details.

All driver functions require the base memory address of the w3_iic_eeprom pcore. This address is set in your XPS project. The EDK tools copy this address into a macro in the xparameters.h file when you generate a BSP. The auto-generated macro should be named XPAR_W3_IIC_EEPROM_0_BASEADDR (assuming your pcore instance is named w3_iic_eeprom_0, as in the example above).

//Define our own macro, in case EDK changes its naming scheme in the future
// Assumes pcore instance is named w3_iic_eeprom_0; confirm in xparameters.h

int x;
u32 board_sn;

//Initialize the EEPROM controller at boot
iic_eeprom_init(EEPROM_BASEADDR, 0x64);

//Write a value to the EEPROM (set EEPROM byte address 2345 to 182)
x = iic_eeprom_writeByte(EEPROM_BASEADDR, 2345, 182);
if(x != 0) xil_printf("EEPROM Write Error!\n");

//Read the value back from EEPROM
x = iic_eeprom_readByte(EEPROM_BASEADDR, 2345);
if(x != 182) xil_printf("EEPROM Read Error (read %d, should be 182)!\n", x);

//Read the WARP v3 board serial number from the EEPROM
board_sn = w3_eeprom_readSerialNum(EEPROM_BASEADDDR);
xil_printf("Board s/n: W3-a-%05d\n", board_sn);


The full hardware and software source code is available in the repository: PlatformSupport/CustomPeripherals/pcores/w3_iic_eeprom_v1_00_b. The VHDL, Verilog and C source code are made available under the WARP license.

The HDL for w3_iic_eeprom incorporates the excellent OpenCores I2C controller core. The unmodified code for the version of the OpenCores code used in this core is included in the opencores_src subdirectory of the w3_iic_eeprom pcore. Refer to the comments in i2c_master_top.v for the author's copyright and warranty notice.

Last modified 5 years ago Last modified on Aug 11, 2012, 9:39:22 PM