wiki:howto/SD_Config

Version 1 (modified by murphpo, 12 years ago) (diff)

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FPGA Configuration via SD Cards

The WARP v3 board includes an SD card slot and CPLD tied to the Virtex-6 FPGA's dedicated configuration pins. Together these circuits enable configuring the FPGA using bitstreams stored on the SD card. For more details on the hardware design, refer to the [HardwareUsersGuides/WARPv3/FPGAConfig WARP v3 user guide].

The basic steps for SD card configuration:

  1. Generate a valid bitstream (.bit file) for the Virtex-6 FPGA
  2. Convert the .bit file into a correctly-formatted .bin file
  3. Copy the .bin file to the correct location on the SD card

Each step is discussed in detail below.

Generating the .bit file

A .bit file is the final output of the Xilinx ISE hardware synthesis and implementation processes. Before you can use the SD card for configuration, you must generate a valid .bit file for the FPGA on your board. You must have a valid .bit file before proceeding with the steps below.

Startup Clock

The .bit file stores both your design and various options which control the startup process of the FPGA itself. One startup option critical to configuration via the SD card is the "Startup Clock". For SD card configuration, the startup clock must be CCLK. All Xilinx tools rely on the bitgen program to create .bit files. However the tools use different methods to configure bitgen.

To set the startup clock:

ISE: Right-click on the "Generate Programming File" process and choose "Process Properties". Click "Startup Options", then change "FPGA Start-Up Clock" to "CCLK". The Startup Options should look like this:

Click OK and re-run the "Generate Programming File" process.

XPS: Switch to the Project tab and open the file "bitgen.ut". Replace the file contents with this one line:

-g StartupClk:Cclk

The updated bitgen.ut should look like:

Save the file and re-run the "Generate Bitstream" process.

SDK: The SDK uses the system.bit file generated by the source XPS project. You must set the Startup Clock option in the original XPS project, then re-export the XPS hardware design to your SDK workspace. The bitstreams included in all WARP reference projects are already configured correctly.

Binary Format

Once you have a valid .bit file with the correct "Startup Clock" option, it must be converted to a .bit ("binary" format) file. Again, the method depends on your design flow.

ISE: Right-click on the "Generate Programming File" process and choose "Process Properties". Click "General Options", then check "Create Binary Configuration File". Click OK and re-run the "Generate Programming File" process. This will create a new .bin file in the same directory as the .bit file.

XPS: Remember that the XPS-generated system.bit does not include any software application. You can generate a .bin file in XPS, but it's not very useful. We recommend using the SDK steps below to generate a .bin version of the download.bit bitstream which includes hardware and software.

But, for the sake of completeness, to generate system.bin in XPS, open "bitgen.ut" and add the line:

-g Binary:Yes
}}}.

'''SDK''': Unfortunately the SDK does not include any easy way to generate a .bin file. The SDK can generate download.bit, the bitstream which includes hardware and software designs. But converting download.bit to binary format is a manual two-step process: updating download.bit, then converting download.bit to download.bin.

'''Updating download.bit'''
 1. Update your software design and ensure it compiles successfully.
 1. From the Xilinx Tools menu, choose Program FPGA.
 1. The Bitstream and BMM File fields will be automatically populated.
 1. In Software Configuration, choose the software binary you want to use. For example, if your software project is named "MySoftwareProj_sw" you should choose "MySoftwareProj_sw.elf".
 1. Click Program. This will update/generate download.bit.

It's ok if your WARP v3 node is powered off or JTAG isn't connected. This dialog box actually triggers two processes: using data2mem to insert your software binary into the block RAMs represented in the existing system.bit, the using impact to download the new download.bit to the FPGA. The first step will succeed even if the second fails (i.e. because there's no JTAG connection).

'''Converting download.bit'''
 1. In the SDK, choose Xilinx Tools -> Launch Shell.
 1. The new command prompt will start in the SDK workspace directory. CD to the hardware project directory. For example, if you're using the WARP template project, you would run "cd WARPv3_TemplateProject_v0_hw_platform".
 1. Confirm the hardware project directory contains system.bit and download.bit.
 1. Run: {{{promgen -u 0 download.bit -p bin -spi -w}}}
 1. Confirm promgen created/updated the file "download.bin"

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