Changes between Version 1 and Version 2 of howto/SPI_Flash_Config


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Timestamp:
Aug 25, 2012, 11:20:12 PM (8 years ago)
Author:
murphpo
Comment:

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  • howto/SPI_Flash_Config

    v1 v2  
    11= WARP v3: SPI Flash =
    22
    3 == Programming the SPI Flash ==
    4 The SPI flash is programmed via iMPACT. Programming the SPI flash requires two steps- generating the PROM file and writing the PROM file to the flash.
     3The WARP v3 board includes a 128Mb SPI flash memory tied to the configuration interface of the Virtex-6 FPGA. This flash memory can store a bitstream which will be automatically loaded into the FPGA on powerup. For more details on the hardware, refer to the [wiki:HardwareUsersGuides/WARPv3/FPGAConfig WARP v3 User Guide].
    54
    6 The PROM programming file (.mcs file) can be generated via the iMPACT GUI or with the promgen command.
     5Using the SPI flash for configuration requires 4 steps:
     6 1. Select the SPI flash for configuration via the config DIP switch
     7 1. Preparing your .bit file for conversion
     8 1. Convert your .bit file to a .mcs file
     9 1. Program the SPI flash with your .mcs file
     10
     11These processes are detailed below.
     12
     13These instructions have been tested with Xilinx ISE 13.4.
     14
     15== Selecting the SPI Flash ==
     16Set the left-most switch in the configuration DIP switch to 1. Refer to the [wiki:HardwareUsersGuides/WARPv3/FPGAConfig WARP v3 User Guide] for details.
     17
     18== Preparing the .bit file ==
     19The FPGA uses Master SPI mode when loading a bitstream from the SPI flash. In this mode the FPGA generates the configuration clock signal and drives it to the CCLK pin. The CCLK pin is routed to the SPI serial clock input. A faster CCLK will result in a faster configuration process.
     20
     21The CCLK frequency is specified in the .bit file and is preserved when generating the .mcs file (as described above). You can change the CCLK frequency via the {{{-g ConfigRate}}} bitgen option. We have successfully tested CCLK frequencies up to 33MHz. Higher frequencies will sometimes work. However the FPGA-generated CCLK frequency is specified as ±55%, so higher nominal frequencies may violate the SPI flash max frequency of 54MHz.
     22
     23To set the CCLK frequency to 33MHz:
     24 * ISE: open the Generate Programming File properties and change Configuration Options -> ConfigRate to 33.
     25 * XPS: edit Project -> bitgen.ut, add a line:
     26{{{
     27-g ConfigRate:33
     28}}}
     29
     30If you're using the SDK, you must update and re-export the bitstream from XPS for the ConfigRate to take effect.
     31
     32All the WARP reference and template designs are configured for ConfigRate of 33MHz by default.
     33
     34== Creating the .mcs File ==
     35You must convert your .bit file to a .mcs file before it can be written to the SPI flash. There are two methods for this: the iMPACT GUI or on the command line with promgen.
    736
    837'''To generate the PROM programming file via the iMPACT GUI:'''
     
    2958}}}
    3059
     60== Programming the SPI Flash ==
     61You must use iMPACT to program the SPI flash. This flash programming process employs a Xilinx-provided FPGA design which connects the FPGA's JTAG port with the SPI flash pins. As a result, running this process re-configures the Virtex-6 FPGA, losing whatever configuration may be loaded.
     62
    3163'''To write the .mcs file to the SPI flash:'''
    3264 1. Connect a programming cable to the FPGA JTAG connector (J14)
     
    4274 1. Click '''OK'''
    4375
    44 iMPACT will now begin writing your .mcs file to the SPI flash. This process is slow, typically requiring 3+ minutes. Watch the iMPACT GUI and console for status and error messages.
     76iMPACT will now begin writing your .mcs file to the SPI flash. This process is slow, typically lasting 5+ minutes (yes, minutes; we have no idea why Xilinx's implementation of JTAG->SPI is so slow). Watch the iMPACT GUI and console for status and error messages.
    4577
    4678When the programming process completes the FPGA will initiate a configuration cycle from the flash. You will see the green '''STAT''' LED glow at half intensity as the FPGA reads the configuration file. The LED will illuminate fully when configuration completes.
    4779
    48 === Configuration Clock Frequency ===
    49 The FPGA uses Master SPI mode when loading a bitstream from the SPI flash. In this mode the FPGA generates the configuration clock signal and drives it to the CCLK pin. The CCLK pin is routed to the SPI serial clock input. A faster CCLK will result in a faster configuration process.
    50 
    51 The CCLK frequency is specified in the .bit file and is preserved when generating the .mcs file (as described above). You can change the CCLK frequency via the {{{-g ConfigRate}}} bitgen option. We have successfully tested CCLK frequencies up to 33MHz. Higher frequencies will sometimes work. However the FPGA-generated CCLK frequency is specified as ±55%, so higher nominal frequencies may violate the SPI flash max frequency of 54MHz.
    52 
    53 To set the CCLK frequency to 33MHz:
    54  * ISE: open the Generate Programming File properties and change Configuration Options -> ConfigRate to 33.
    55  * XPS: edit Project -> bitgen.ut, add a line:
    56 {{{
    57 -g ConfigRate:33
    58 }}}
    59 
    60 You will need to re-generate the .mcs file and re-program the SPI flash if you change the CCLK frequency.