wiki:howto/XPS_to_PlanAhead

XPS to PlanAhead Project Conversion

The following process describes how to create a PlanAhead project from an existing XPS project. This process has been tested in ISE 14.4 and 14.7. It is likely that this flow is different or broken in earlier versions of the Xilinx tools.

Overview

The steps below use a few placeholder names:

  • <src_xps_proj>: root of your existing XPS project. This is the folder containing your system.xmp and system.mhs files.
  • <pa_proj_dir>: root of your new PlanAhead project. This folder should be empty before creating the PlanAhead project.
  • PA_PROJ: name of your new PlanAhead project

Creating the PlanAhead Project

  1. Launch Xilinx PlanAhead
  2. Select Create New Project, click Next
  3. Enter your choice of project name. We'll refer to this as PA_PROJ below
  4. Enter a project location. We'll refer to this as <pa_proj_dir> below
  5. Click Next
  6. Select RTL Project and check Do not specify sources at this time
  7. Click Next, then select your FPGA device (xc6vlx240tff1156-2 for WARP v3 projects)
  8. Click Next then Finish

You should now see the PlanAhead workspace.

Creating the PlanAhead XPS Source

  1. Start in the PlanAhead workspace and find the Sources tab, probably in the upper-left of the Project Manager sub-pane.
  2. Right-click and select Add Sources
  3. Select Add or Create Embedded Sources then click Next
  4. Click Create Sub-Design
  5. Enter a top-level module name. We'll use xps_top here.
  6. Click Ok, then Finish
  7. XPS will launch on top of the PlanAhead workspace. You should see a dialog box asking: "This project appears to be a blank project. Do you want to create a Base System using the BSB Wizard?". Click No.
  8. You should now see a blank XPS project:

  1. Minimize the XPS window but do not close XPS

At this point you have two XPS projects. The XPS project inside the PlanAhead project is blank and must be updated with the hardware design from your original XPS project.

  1. Navigate to <pa_proj_dir>/PA_PROJ.srcs/sources_1/edk/xps_top. This is the root of your new XPS project.
  2. From your source XPS project folder, copy the following into the new XPS project folder:
    • The contents of the pcores, drivers and sw_services folders (if they exist)
    • Any data/*.prj files, such as data/DDR3_SODIMM_mig_saved.prj in Mango reference designs
    • Do not copy any UCF files from your old project. These will be handled below
  3. Copy and paste the contents of the old MHS file into the new MHS file
    • Copy from <src_xps_proj>/system.mhs
    • Paste into <pa_proj_dir>/PA_PROJ.srcs/sources_1/edk/xps_top/xps_top.mhs
  4. Save the modified xps_top.mhs, then close XPS.

If XPS throws an error, you probably forgot to copy cores/code from the old XPS project. Also double check that your edk_user_repository is up to date and that the edk_user_repository is in the Global Peripheral Repository Search Path in the XPS preferences (see edk_user_repository for more).

HDL Wrapper

At this point your PlanAhead project has one source, the XPS project. Unfortunately PlanAhead does not support XPS projects as top-level modules for implementation.

  1. In the PlanAhead Sources tab right-click on your XPS source and select Create Top HDL
  2. The sources tab will update to show a new hierarchy:

  1. Notice that the XPS project instance has been renamed xps_top_i - this is important for the next step

Constraints

You must now add a constraints file to the PlanAhead Project. Your constraints will be based on the top-level constraints from your source XPS project.

  1. In the PlanAhead workspace Sources tab, right-click and select 'Add Sources
  2. Select Add or Create Constraints then click Next
  3. Click Create File and choose a filename. We'll use xps_constraints here.
  4. Click Ok, then Finish
  5. In the Sources tab expand the Constraints/constrs_1 folder and double click your UCF file
  6. In another text editor open your source XPS project constraints file <src_xps_proj>/data/system.ucf
  7. Copy and paste the old file contents into the new UCF file in PlanAhead, then save the new file

At this point your PlanAhead project constraints match the source XPS project constraints exactly.

The PlanAhead-wrapped XPS project uses the same net names when connecting XPS ports to top-level pins. For constraints which refer to top-level nets, like NET clk_in LOC = SOME_PIN, no changes are required.

For constraints which refer to nets or instances by hierarchical name, the new UCF must be updated to reflect the XPS project instance name and hierarchy.

For example, assume your original XPS project system.ucf had the following constraints:

#XPS system.ucf

#Top-level ports
NET "led_red"    LOC = A1;
NET "led_green"  LOC = A2;
NET "led_yellow" LOC = A3;

#TEMAC loc
INST "ETH_MAC*v6_emac" LOC = "TEMAC_X0Y0";

The updated constraints for the PlanAhead xps_constraints.ucf file would be:

#PlanAhead xps_constraints.ucf

#Top-level ports
NET "led_red"    LOC = A1;
NET "led_green"  LOC = A2;
NET "led_yellow" LOC = A3;

#TEMAC loc
INST "xps_top_i/ETH_MAC*v6_emac" LOC = "TEMAC_X0Y0";

Notice the xps_top_i prefix on the TEMAC LOC constraint. Because this constraint refers to a design object by hierarchical name the path must include the new XPS project instance name.

Implementation Options

Once your constraints are updated the design is ready to implement. There are many options in the PlanAhead implementation flow. A few recommendations are listed below. Refer to the PlanAhead user guide (Xilinx UG632).

Synthesis Settings The following settings have worked well in our experience:

Implementation Settings The following settings have worked well in our experience:

  • Translate:
  • MAP:
  • PAR:
  • BITGEN:

Implementing the Design

Click Run Implementation. This will start the full synthesis and implementation flow. The run time depends on the complexity of your design. For a complex design like the 802.11 Reference Design the start-to-finish implementation time is 2+ hours.

Additional Resources

Last modified 6 years ago Last modified on Mar 4, 2014, 9:19:03 PM

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